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picorv32
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Added REGS_INIT_ZERO parameter

This commit is contained in:
Clifford Wolf 2016-08-24 15:20:23 +02:00
parent bec8d6a6b9
commit 8043c90a04
2 changed files with 16 additions and 0 deletions
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5
README.md
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@ -256,6 +256,11 @@ Set this to 0 to disable support for the `timer` instruction.
Support for the timer is always disabled when ENABLE_IRQ is set to 0. Support for the timer is always disabled when ENABLE_IRQ is set to 0.
#### REGS_INIT_ZERO (default = 0)
Set this to 1 to initialize all registers to zero (using a Verilog `initial` block).
This can be useful for simulation or formal verification.
#### MASKED_IRQ (default = 32'h 0000_0000) #### MASKED_IRQ (default = 32'h 0000_0000)
A 1 bit in this bitmask corresponds to a permanently disabled IRQ. A 1 bit in this bitmask corresponds to a permanently disabled IRQ.

11
picorv32.v
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@ -58,6 +58,7 @@ module picorv32 #(
parameter [ 0:0] ENABLE_IRQ = 0, parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1, parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1, parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
@ -135,6 +136,14 @@ module picorv32 #(
reg [31:0] irq_pending; reg [31:0] irq_pending;
reg [31:0] timer; reg [31:0] timer;
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`ifdef DEBUGREGS `ifdef DEBUGREGS
wire [31:0] dbg_reg_x0 = cpuregs[0]; wire [31:0] dbg_reg_x0 = cpuregs[0];
wire [31:0] dbg_reg_x1 = cpuregs[1]; wire [31:0] dbg_reg_x1 = cpuregs[1];
@ -1882,6 +1891,7 @@ module picorv32_axi #(
parameter [ 0:0] ENABLE_IRQ = 0, parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1, parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1, parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
@ -1983,6 +1993,7 @@ module picorv32_axi #(
.ENABLE_IRQ (ENABLE_IRQ ), .ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ), .MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ), .LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ), .PROGADDR_RESET (PROGADDR_RESET ),