mirror of https://github.com/YosysHQ/picorv32.git
Be more explicit about single register file write port
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picorv32.v
20
picorv32.v
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@ -1063,6 +1063,9 @@ module picorv32 #(
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if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
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end
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reg cpuregs_write;
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reg [31:0] cpuregs_wrdata;
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reg set_mem_do_rinst;
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reg set_mem_do_rdata;
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reg set_mem_do_wdata;
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@ -1169,6 +1172,8 @@ module picorv32 #(
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trap <= 0;
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reg_sh <= 'bx;
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reg_out <= 'bx;
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cpuregs_write = 0;
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cpuregs_wrdata = 'bx;
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set_mem_do_rinst = 0;
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set_mem_do_rdata = 0;
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set_mem_do_wdata = 0;
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@ -1264,25 +1269,32 @@ module picorv32 #(
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latched_branch: begin
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current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) : reg_next_pc;
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
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cpuregs[latched_rd] <= reg_pc + (latched_compr ? 2 : 4);
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cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
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cpuregs_write = 1;
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end
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latched_store && !latched_branch: begin
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`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
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cpuregs[latched_rd] <= latched_stalu ? alu_out_q : reg_out;
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cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
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cpuregs_write = 1;
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end
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ENABLE_IRQ && irq_state[0]: begin
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cpuregs[latched_rd] <= current_pc | latched_compr;
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cpuregs_wrdata = current_pc | latched_compr;
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cpuregs_write = 1;
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current_pc = PROGADDR_IRQ;
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irq_active <= 1;
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mem_do_rinst <= 1;
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end
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ENABLE_IRQ && irq_state[1]: begin
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eoi <= irq_pending & ~irq_mask;
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cpuregs[latched_rd] <= irq_pending & ~irq_mask;
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cpuregs_wrdata = irq_pending & ~irq_mask;
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cpuregs_write = 1;
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next_irq_pending = next_irq_pending & irq_mask;
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end
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endcase
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if (cpuregs_write)
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cpuregs[latched_rd] <= cpuregs_wrdata;
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if (ENABLE_TRACE && latched_trace) begin
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latched_trace <= 0;
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trace_valid <= 1;
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