mirror of https://github.com/YosysHQ/picorv32.git
Renamed testbench_slow_mem to testbench_nola (no look ahead)
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parent
e403c950b0
commit
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@ -10,6 +10,8 @@
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/dhrystone/dhry.map
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/dhrystone/testbench.vvp
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/dhrystone/testbench.vcd
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/dhrystone/testbench_nola.vvp
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/dhrystone/testbench_nola.vcd
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/dhrystone/timing.vvp
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/dhrystone/timing.txt
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/dhrystone/*.d
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@ -13,8 +13,8 @@ endif
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test: testbench.vvp dhry.hex
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vvp -N testbench.vvp
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test_slow_mem: testbench_slow_mem.vvp dhry.hex
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vvp -N testbench_slow_mem.vvp
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test_nola: testbench_nola.vvp dhry.hex
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vvp -N testbench_nola.vvp
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timing: timing.txt
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grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
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@ -27,9 +27,9 @@ testbench.vvp: testbench.v ../picorv32.v
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iverilog -o testbench.vvp testbench.v ../picorv32.v
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chmod -x testbench.vvp
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testbench_slow_mem.vvp: testbench_slow_mem.v ../picorv32.v
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iverilog -o testbench_slow_mem.vvp testbench_slow_mem.v ../picorv32.v
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chmod -x testbench_slow_mem.vvp
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testbench_nola.vvp: testbench_nola.v ../picorv32.v
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iverilog -o testbench_nola.vvp testbench_nola.v ../picorv32.v
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chmod -x testbench_nola.vvp
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timing.vvp: testbench.v ../picorv32.v
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iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v
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@ -57,7 +57,7 @@ endif
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dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
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clean:
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_slow_mem.vvp
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_nola.vvp
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.PHONY: test clean
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@ -1,3 +1,5 @@
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// A version of the dhrystone test bench that isn't using the look-ahead interface
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`timescale 1 ns / 1 ps
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module testbench;
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@ -79,7 +81,7 @@ module testbench;
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end
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initial begin
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$dumpfile("testbench_slow_mem.vcd");
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$dumpfile("testbench_nola.vcd");
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$dumpvars(0, testbench);
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end
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