mirror of https://github.com/YosysHQ/picorv32.git
Added generic "make check-<solver>" rule
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parent
d5b7e9e175
commit
8bfd7c166b
12
Makefile
12
Makefile
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@ -19,13 +19,11 @@ testbench.vcd: testbench.vvp firmware/firmware.hex
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view: testbench.vcd
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view: testbench.vcd
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gtkwave $< testbench.gtkw
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gtkwave $< testbench.gtkw
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check-z3: check.smt2
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check: check-yices
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yosys-smtbmc -s z3 -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s z3 -t 30 --dump-vcd check.vcd -i check.smt2
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check-yices: check.smt2
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check-%: check.smt2
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yosys-smtbmc -s yices -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s yices -t 30 --dump-vcd check.vcd -i check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd -i check.smt2
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check.smt2: picorv32.v
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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@ -137,5 +135,5 @@ clean:
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench.vcd testbench.trace
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testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench.vcd testbench.trace
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.PHONY: test view test_sp test_axi test_synth check-z3 check-yices download-tools build-tools toc clean
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.PHONY: test view test_sp test_axi test_synth download-tools build-tools toc clean
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