mirror of https://github.com/YosysHQ/picorv32.git
Using riscv32-unknown-elf- toolchain
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6
Makefile
6
Makefile
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@ -3,7 +3,7 @@ TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
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FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve.o firmware/multest.o firmware/stats.o
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GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
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GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
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TOOLCHAIN_PREFIX = riscv64-unknown-elf-
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TOOLCHAIN_PREFIX = riscv32-unknown-elf-
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test: testbench.exe firmware/firmware.hex
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vvp -N testbench.exe
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@ -65,13 +65,13 @@ firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
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chmod -x $@
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firmware/start.o: firmware/start.S
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$(TOOLCHAIN_PREFIX)gcc -c -m32 -o $@ $<
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$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IMXcustom -o $@ $<
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firmware/%.o: firmware/%.c
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$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32I -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
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tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
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$(TOOLCHAIN_PREFIX)gcc -c -m32 -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
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$(TOOLCHAIN_PREFIX)gcc -c -m32 -march=RV32IM -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
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-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
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toc:
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@ -5,6 +5,8 @@ PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 is a CPU core that implements the [RISC-V RV32I Instruction Set](http://riscv.org/).
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Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools).
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The examples bundled with PicoRV32 (such as the firmware for `make test`) expect a `riscv32-unknown-elf-` toolchain
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(see [build instructions below](#building-a-pure-rv32i-toolchain)) installed in `$PATH`.
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PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
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(a license that is similar in terms to the MIT license or the 2-clause BSD license).
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@ -1,6 +1,7 @@
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OBJS = start.o dhry_1.o dhry_2.o stdlib.o
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CFLAGS = -MD -O3 -m32 -march=RV32I -ffreestanding -nostdlib -DTIME -DRISCV
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TOOLCHAIN_PREFIX = riscv32-unknown-elf-
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test: testbench.exe dhry.hex
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vvp -N testbench.exe
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@ -21,18 +22,20 @@ dhry.hex: dhry.bin ../firmware/makehex.py
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python3 ../firmware/makehex.py $< 16384 > $@
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dhry.bin: dhry.elf
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riscv64-unknown-elf-objcopy -O binary $< $@
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$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
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chmod -x $@
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dhry.elf: $(OBJS) ../firmware/sections.lds
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riscv64-unknown-elf-gcc $(CFLAGS) -Wl,-Bstatic,-T,../firmware/sections.lds,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc
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$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) -Wl,-Bstatic,-T,../firmware/sections.lds,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc
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chmod -x $@
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%.o: %.c
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riscv64-unknown-elf-gcc -c $(CFLAGS) $<
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$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) $<
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%.o: %.S
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riscv64-unknown-elf-gcc -c $(CFLAGS) $<
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$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) $<
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dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
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clean:
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd timing.exe timing.txt
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