mirror of https://github.com/YosysHQ/picorv32.git
README.md: drop dead tool reference
The URL https://riscv.org/software-status/ doesn't work anymore and for all modern distros, the supplied tools will work just fine. I suspect most will find this the easier path.
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@ -6,12 +6,11 @@ PicoRV32 is a CPU core that implements the [RISC-V RV32IMC Instruction Set](http
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It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally
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It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally
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contains a built-in interrupt controller.
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contains a built-in interrupt controller.
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Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](https://riscv.org/software-status/).
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The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in `/opt/riscv32i[m][c]`. See
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the [build instructions below](#building-a-pure-rv32i-toolchain) for details.
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Many Linux distributions now include the tools for RISC-V (for example
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Many Linux distributions now include the tools for RISC-V (for example
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Ubuntu 20.04 has `gcc-riscv64-unknown-elf`). To compile using those set
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Ubuntu 20.04 has `gcc-riscv64-unknown-elf`). To compile using those set
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`TOOLCHAIN_PREFIX` accordingly (eg. `make TOOLCHAIN_PREFIX=riscv64-unknown-elf-`).
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`TOOLCHAIN_PREFIX` accordingly (eg. `make TOOLCHAIN_PREFIX=riscv64-unknown-elf-`).
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Alternatively, see the [build instructions below](#building-a-pure-rv32i-toolchain)
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to build the toolsfrom source.
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PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
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PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
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(a license that is similar in terms to the MIT license or the 2-clause BSD license).
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(a license that is similar in terms to the MIT license or the 2-clause BSD license).
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