Vivado "system" example

scripts/vivado/.gitignore

@@ -1,4 +1,18 @@
+.Xil/
+firmware.bin
+firmware.elf
+firmware.hex
+firmware.map
 synth_*.log
 synth_*.mmi
 synth_*.bit
+synth_system.v
+table.txt
 tab_*/
+webtalk.jou
+webtalk.log
+webtalk_*.jou
+webtalk_*.log
+xelab.*
+xsim.*
+xvlog.*

scripts/vivado/Makefile

@@ -1,8 +1,26 @@
 
-export VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado
+VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado
+XVLOG = /opt/Xilinx/Vivado/2015.1/bin/xvlog
+XELAB = /opt/Xilinx/Vivado/2015.1/bin/xelab
+GLBL = /opt/Xilinx/Vivado/2015.1/data/verilog/src/glbl.v
+TOOLCHAIN_PREFIX = riscv64-unknown-elf-
+
+export VIVADO
 
 help:
-	@echo "Usage: make {synth_speed|synth_area|synth_soc}"
+	@echo ""
+	@echo "Simple synthesis tests:"
+	@echo "  make synth_area_{small|regular|large}"
+	@echo "  make synth_speed"
+	@echo ""
+	@echo "Example system:"
+	@echo "  make synth_system"
+	@echo "  make sim_system"
+	@echo ""
+	@echo "Timing and Utilization Evaluation:"
+	@echo "  make table.txt"
+	@echo "  make area"
+	@echo ""
 
 synth_%:
 	rm -f $@.log
@@ -11,6 +29,19 @@ synth_%:
 	-grep -B4 -A10 'Slice LUTs' $@.log
 	-grep -B1 -A9 ^Slack $@.log && echo
 
+synth_system: firmware.hex
+
+sim_system:
+	$(XVLOG) system_tb.v synth_system.v
+	$(XVLOG) $(GLBL)
+	$(XELAB) -L unifast_ver -L unisims_ver -R system_tb glbl
+
+firmware.hex: firmware.S firmware.c firmware.lds
+	$(TOOLCHAIN_PREFIX)gcc -Os -m32 -ffreestanding -nostdlib -o firmware.elf firmware.S firmware.c \
+		 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug -lgcc
+	$(TOOLCHAIN_PREFIX)objcopy -O binary firmware.elf firmware.bin
+	python3 ../../firmware/makehex.py firmware.bin > firmware.hex
+
 tab_%/results.txt:
 	bash tabtest.sh $@
 
@@ -24,3 +55,8 @@ table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_x
 table.txt:
 	bash table.sh > table.txt
 
+clean:
+	rm -rf .Xil/ firmware.bin firmware.elf firmware.hex firmware.map synth_*.log
+	rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/ webtalk.jou
+	rm -rf webtalk.log webtalk_*.jou webtalk_*.log xelab.* xsim.* xvlog.*
+

scripts/vivado/firmware.S

@@ -0,0 +1,12 @@
+.section .init
+.global main
+
+/* set stack pointer */
+lui sp, %hi(16*1024)
+addi sp, sp, %lo(16*1024)
+
+/* call main */
+jal ra, main
+
+/* break */
+sbreak

scripts/vivado/firmware.c

@@ -0,0 +1,14 @@
+void putc(char c)
+{
+	*(volatile char*)0x10000000 = c;
+}
+
+void puts(const char *s)
+{
+	while (*s) putc(*s++);
+}
+
+void main()
+{
+	puts("Hello World!\n");
+}

scripts/vivado/firmware.lds

@@ -0,0 +1,11 @@
+SECTIONS {
+	.memory : {
+		. = 0x000000;
+		*(.init);
+		*(.text);
+		*(*);
+		. = ALIGN(4);
+		end = .;
+	}
+}
+

scripts/vivado/synth_soc.tcl

@@ -1,17 +0,0 @@
-
-read_verilog soc_top.v
-read_verilog ../../picorv32.v
-read_xdc synth_soc.xdc
-
-synth_design -part xc7a35t-cpg236-1 -top soc_top
-opt_design
-place_design
-route_design
-
-report_utilization
-report_timing
-
-write_verilog -force synth_soc.v
-write_bitstream -force synth_soc.bit
-# write_mem_info -force synth_soc.mmi
-

scripts/vivado/synth_system.tcl

@@ -0,0 +1,17 @@
+
+read_verilog system.v
+read_verilog ../../picorv32.v
+read_xdc synth_system.xdc
+
+synth_design -part xc7a35t-cpg236-1 -top system
+opt_design
+place_design
+route_design
+
+report_utilization
+report_timing
+
+write_verilog -force synth_system.v
+write_bitstream -force synth_system.bit
+# write_mem_info -force synth_system.mmi
+

scripts/vivado/system.v

@@ -1,6 +1,6 @@
 `timescale 1 ns / 1 ps
 
-module soc_top (
+module system (
 	input            clk,
 	input            resetn,
 	output           trap,
@@ -43,7 +43,7 @@ module soc_top (
 	);
 
 	reg [31:0] memory [0:MEM_SIZE-1];
-	// initial $readmemh("firmware.hex", memory);
+	initial $readmemh("firmware.hex", memory);
 
 	assign mem_ready = 1;
 

scripts/vivado/system_tb.v

@@ -0,0 +1,34 @@
+`timescale 1 ns / 1 ps
+
+module system_tb;
+	reg clk = 1;
+	always #5 clk = ~clk;
+
+	reg resetn = 0;
+	initial begin
+		repeat (100) @(posedge clk);
+		resetn <= 1;
+	end
+
+	wire trap;
+	wire [7:0] out_byte;
+	wire out_byte_en;
+
+	system uut (
+		.clk        (clk        ),
+		.resetn     (resetn     ),
+		.trap       (trap       ),
+		.out_byte   (out_byte   ),
+		.out_byte_en(out_byte_en)
+	);
+
+	always @(posedge clk) begin
+		if (resetn && out_byte_en) begin
+			$write("%c", out_byte);
+			$fflush;
+		end
+		if (resetn && trap) begin
+			$finish;
+		end
+	end
+endmodule