mirror of https://github.com/YosysHQ/picorv32.git
Split out verilator-incompatible code to top-level testbench
Verilator doesn't handle verilog code that deals with time, such as delayed signals or the repeat task. Clock and reset generation are therefore moved to a separate file that can be replaced by a verilator module. VCD generation is also affected by this.
This commit is contained in:
Olof Kindgren
parent
8343315aa7
commit
9591ae9f7d
8
Makefile
8
Makefile
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@ -33,12 +33,12 @@ test_axi: testbench.exe firmware/firmware.hex
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test_synth: testbench_synth.exe firmware/firmware.hex
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vvp -N testbench_synth.exe
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testbench.exe: testbench.v axi4_memory.v picorv32.v
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iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v axi4_memory.v picorv32.v
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testbench.exe: testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
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iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
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chmod -x testbench.exe
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testbench_sp.exe: testbench.v axi4_memory.v picorv32.v
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iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v axi4_memory.v picorv32.v
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testbench_sp.exe: testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
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iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
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chmod -x testbench_sp.exe
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testbench_synth.exe: testbench.v synth.v
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@ -0,0 +1,118 @@
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// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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module picorv32_wrapper #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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) (
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input clk,
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input resetn
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);
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wire trap;
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reg [31:0] irq;
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always @* begin
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irq = 0;
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irq[4] = &uut.picorv32_core.count_cycle[12:0];
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irq[5] = &uut.picorv32_core.count_cycle[15:0];
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end
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wire mem_axi_awvalid;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [ 2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [ 3:0] mem_axi_wstrb;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [ 2:0] mem_axi_arprot;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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wire [31:0] mem_axi_rdata;
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axi4_memory #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) mem (
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.clk (clk ),
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.mem_axi_awvalid (mem_axi_awvalid ),
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.mem_axi_awready (mem_axi_awready ),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid (mem_axi_arvalid ),
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.mem_axi_arready (mem_axi_arready ),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata )
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);
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picorv32_axi #(
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`ifdef SP_TEST
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.ENABLE_REGS_DUALPORT(0),
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`endif
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.ENABLE_MUL(1),
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.ENABLE_IRQ(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_axi_awvalid(mem_axi_awvalid),
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.mem_axi_awready(mem_axi_awready),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid(mem_axi_arvalid),
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.mem_axi_arready(mem_axi_arready),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.irq (irq )
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);
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initial $readmemh("firmware/firmware.hex", mem.memory);
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integer cycle_counter;
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always @(posedge clk) begin
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cycle_counter <= resetn ? cycle_counter + 1 : 0;
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if (resetn && trap) begin
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`ifndef VERILATOR
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repeat (10) @(posedge clk);
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`endif
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$display("TRAP after %1d clock cycles", cycle_counter);
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$finish;
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end
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end
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endmodule
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106
testbench.v
106
testbench.v
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@ -15,14 +15,6 @@ module testbench #(
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reg clk = 1;
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reg resetn = 0;
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reg [31:0] irq;
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wire trap;
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always @* begin
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irq = 0;
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irq[4] = &uut.picorv32_core.count_cycle[12:0];
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irq[5] = &uut.picorv32_core.count_cycle[15:0];
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end
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always #5 clk = ~clk;
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@ -31,88 +23,6 @@ module testbench #(
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resetn <= 1;
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end
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wire mem_axi_awvalid;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [ 2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [ 3:0] mem_axi_wstrb;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [ 2:0] mem_axi_arprot;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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wire [31:0] mem_axi_rdata;
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axi4_memory #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) mem (
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.clk (clk ),
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.mem_axi_awvalid (mem_axi_awvalid ),
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.mem_axi_awready (mem_axi_awready ),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid (mem_axi_arvalid ),
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.mem_axi_arready (mem_axi_arready ),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata )
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);
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picorv32_axi #(
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`ifdef SP_TEST
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.ENABLE_REGS_DUALPORT(0),
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`endif
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.ENABLE_MUL(1),
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.ENABLE_IRQ(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_axi_awvalid(mem_axi_awvalid),
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.mem_axi_awready(mem_axi_awready),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid(mem_axi_arvalid),
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.mem_axi_arready(mem_axi_arready),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.irq (irq )
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);
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initial $readmemh("firmware/firmware.hex", mem.memory);
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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@ -123,13 +33,11 @@ module testbench #(
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$finish;
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end
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integer cycle_counter;
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always @(posedge clk) begin
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cycle_counter <= resetn ? cycle_counter + 1 : 0;
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP after %1d clock cycles", cycle_counter);
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$finish;
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end
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end
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picorv32_wrapper #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) top (
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.clk (clk ),
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.resetn (resetn)
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);
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endmodule
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