Added TOC to README

This commit is contained in:
Clifford Wolf 2015-06-30 12:25:05 +02:00
parent 997c5ce341
commit 9d809eb0d9
2 changed files with 16 additions and 1 deletions

View File

@ -56,10 +56,13 @@ tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
riscv64-unknown-elf-gcc -c -m32 -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
toc:
gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
clean:
rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) \
firmware/firmware.{elf,bin,hex,map} synth.v \
testbench{,_sp,_axi,_synth}.exe testbench.vcd
.PHONY: test test_sp test_axi clean
.PHONY: test test_sp test_axi test_sync toc clean

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@ -9,6 +9,18 @@ Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://ris
PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
(a license that is similar in terms to the MIT license or the 2-clause BSD license).
#### Table of Contents
- [Features and Typical Applications](#features-and-typical-applications)
- [Files in this Repository](#files-in-this-repository)
- [Verilog Module Parameters](#verilog-module-parameters)
- [Cycles per Instruction Performance](#cycles-per-instruction-performance)
- [PicoRV32 Native Memory Interface](#picorv32-native-memory-interface)
- [Pico Co-Processor Interface (PCPI)](#pico-co-processor-interface-pcpi)
- [Custom Instructions for IRQ Handling](#custom-instructions-for-irq-handling)
- [Building a pure RV32I Toolchain](#building-a-pure-rv32i-toolchain)
- [Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs](#evaluation-timing-and-utilization-on-xilinx-7-series-fpgas)
Features and Typical Applications
---------------------------------