mirror of https://github.com/YosysHQ/picorv32.git
Added TOC to README
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5
Makefile
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Makefile
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@ -56,10 +56,13 @@ tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
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riscv64-unknown-elf-gcc -c -m32 -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
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-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
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toc:
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gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
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clean:
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) \
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firmware/firmware.{elf,bin,hex,map} synth.v \
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testbench{,_sp,_axi,_synth}.exe testbench.vcd
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.PHONY: test test_sp test_axi clean
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.PHONY: test test_sp test_axi test_sync toc clean
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12
README.md
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README.md
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@ -9,6 +9,18 @@ Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://ris
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PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
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(a license that is similar in terms to the MIT license or the 2-clause BSD license).
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#### Table of Contents
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- [Features and Typical Applications](#features-and-typical-applications)
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- [Files in this Repository](#files-in-this-repository)
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- [Verilog Module Parameters](#verilog-module-parameters)
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- [Cycles per Instruction Performance](#cycles-per-instruction-performance)
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- [PicoRV32 Native Memory Interface](#picorv32-native-memory-interface)
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- [Pico Co-Processor Interface (PCPI)](#pico-co-processor-interface-pcpi)
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- [Custom Instructions for IRQ Handling](#custom-instructions-for-irq-handling)
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- [Building a pure RV32I Toolchain](#building-a-pure-rv32i-toolchain)
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- [Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs](#evaluation-timing-and-utilization-on-xilinx-7-series-fpgas)
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Features and Typical Applications
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---------------------------------
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