mirror of https://github.com/YosysHQ/picorv32.git
Add "make test_rvf"
This commit is contained in:
Clifford Wolf
parent
8db3073ff9
commit
a412d3ea69
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@ -24,6 +24,7 @@
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/testbench_wb.vvp
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/testbench_ez.vvp
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/testbench_sp.vvp
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/testbench_rvf.vvp
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/testbench_synth.vvp
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/testbench.gtkw
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/testbench.vcd
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33
Makefile
33
Makefile
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@ -19,6 +19,9 @@ test: testbench.vvp firmware/firmware.hex
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test_vcd: testbench.vvp firmware/firmware.hex
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vvp -N $< +vcd +trace +noerror
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test_rvf: testbench_rvf.vvp firmware/firmware.hex
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vvp -N $< +vcd +trace +noerror
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test_wb: testbench_wb.vvp firmware/firmware.hex
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vvp -N $<
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@ -31,18 +34,6 @@ test_ez: testbench_ez.vvp
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test_ez_vcd: testbench_ez.vvp
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vvp -N $< +vcd
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check: check-yices
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check-%: check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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-p 'prep -top picorv32 -nordff' \
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-p 'assertpmux -noinit; opt -fast' \
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-p 'write_smt2 -wires check.smt2'
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test_sp: testbench_sp.vvp firmware/firmware.hex
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vvp -N $<
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@ -56,6 +47,10 @@ testbench.vvp: testbench.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_rvf.vvp: testbench.v picorv32.v rvfimon.v
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iverilog -o $@ -D RISCV_FORMAL $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_wb.vvp: testbench_wb.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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@ -72,6 +67,18 @@ testbench_synth.vvp: testbench.v synth.v
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iverilog -o $@ -DSYNTH_TEST $^
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chmod -x $@
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check: check-yices
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check-%: check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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-p 'prep -top picorv32 -nordff' \
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-p 'assertpmux -noinit; opt -fast' \
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-p 'write_smt2 -wires check.smt2'
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synth.v: picorv32.v scripts/yosys/synth_sim.ys
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yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
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@ -155,6 +162,6 @@ clean:
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
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testbench_wb.vvp testbench.vcd testbench.trace
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testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace
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.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean
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48
testbench.v
48
testbench.v
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@ -137,9 +137,11 @@ module picorv32_wrapper #(
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`ifdef RISCV_FORMAL
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wire rvfi_valid;
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wire [7:0] rvfi_order;
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wire [63:0] rvfi_order;
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wire [31:0] rvfi_insn;
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wire rvfi_trap;
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wire rvfi_halt;
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wire rvfi_intr;
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wire [4:0] rvfi_rs1_addr;
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wire [4:0] rvfi_rs2_addr;
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wire [31:0] rvfi_rs1_rdata;
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@ -195,6 +197,8 @@ module picorv32_wrapper #(
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_halt (rvfi_halt ),
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.rvfi_intr (rvfi_intr ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata ),
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@ -214,26 +218,28 @@ module picorv32_wrapper #(
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);
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`ifdef RISCV_FORMAL
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riscv_formal_monitor_rv32ic rvfi_monitor (
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.clock (clk ),
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.reset (!resetn ),
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata(rvfi_rs1_rdata),
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.rvfi_rs2_rdata(rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask(rvfi_mem_rmask),
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.rvfi_mem_wmask(rvfi_mem_wmask),
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.rvfi_mem_rdata(rvfi_mem_rdata),
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.rvfi_mem_wdata(rvfi_mem_wdata)
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picorv32_rvfimon rvfi_monitor (
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.clock (clk ),
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.reset (!resetn ),
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_halt (rvfi_halt ),
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.rvfi_intr (rvfi_intr ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata),
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.rvfi_rs2_rdata (rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask (rvfi_mem_rmask),
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.rvfi_mem_wmask (rvfi_mem_wmask),
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.rvfi_mem_rdata (rvfi_mem_rdata),
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.rvfi_mem_wdata (rvfi_mem_wdata)
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);
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`endif
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