mirror of https://github.com/YosysHQ/picorv32.git
Added picorv32_pcpi_fast_mul core
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Clifford Wolf
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12
README.md
12
README.md
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@ -86,11 +86,12 @@ You are reading it right now.
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This Verilog file contains the following Verilog modules:
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| Module | Description |
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| ----------------------- | ------------------------------------------------------------- |
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| ------------------------ | --------------------------------------------------------------------- |
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| `picorv32` | The PicoRV32 CPU |
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| `picorv32_axi` | The version of the CPU with AXI4-Lite interface |
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| `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite |
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| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions |
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| `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier |
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| `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions |
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Simply copy this file into your project.
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@ -229,6 +230,15 @@ This parameter internally enables PCPI and instantiates the `picorv32_pcpi_mul`
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core that implements the `MUL[H[SU|U]]` instructions. The external PCPI
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interface only becomes functional when ENABLE_PCPI is set as well.
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#### ENABLE_FAST_MUL (default = 0)
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This parameter internally enables PCPI and instantiates the `picorv32_pcpi_fast_mul`
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core that implements the `MUL[H[SU|U]]` instructions. The external PCPI
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interface only becomes functional when ENABLE_PCPI is set as well.
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If both ENABLE_MUL and ENABLE_FAST_MUL are set then the ENABLE_MUL setting
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will be ignored and the fast multiplier core will be instantiated.
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#### ENABLE_DIV (default = 0)
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This parameter internally enables PCPI and instantiates the `picorv32_pcpi_div`
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92
picorv32.v
92
picorv32.v
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@ -56,6 +56,7 @@ module picorv32 #(
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_FAST_MUL = 0,
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parameter [ 0:0] ENABLE_DIV = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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@ -113,7 +114,7 @@ module picorv32 #(
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localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
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localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
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localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_DIV;
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localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
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localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
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localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
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@ -207,7 +208,20 @@ module picorv32 #(
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reg pcpi_int_wait;
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reg pcpi_int_ready;
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generate if (ENABLE_MUL) begin
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generate if (ENABLE_FAST_MUL) begin
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picorv32_pcpi_fast_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_mul_wr ),
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.pcpi_rd (pcpi_mul_rd ),
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.pcpi_wait (pcpi_mul_wait ),
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.pcpi_ready(pcpi_mul_ready )
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);
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end else if (ENABLE_MUL) begin
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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@ -250,8 +264,8 @@ module picorv32 #(
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always @* begin
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pcpi_int_wr = 0;
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pcpi_int_rd = 1'bx;
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pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, ENABLE_MUL && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
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pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, ENABLE_MUL && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
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pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
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pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
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(* parallel_case *)
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case (1'b1)
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@ -259,7 +273,7 @@ module picorv32 #(
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pcpi_int_wr = pcpi_wr;
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pcpi_int_rd = pcpi_rd;
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end
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ENABLE_MUL && pcpi_mul_ready: begin
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(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
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pcpi_int_wr = pcpi_mul_wr;
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pcpi_int_rd = pcpi_mul_rd;
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end
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@ -1856,6 +1870,72 @@ module picorv32_pcpi_mul #(
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end
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endmodule
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module picorv32_pcpi_fast_mul (
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input clk, resetn,
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input pcpi_valid,
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input [31:0] pcpi_insn,
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input [31:0] pcpi_rs1,
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input [31:0] pcpi_rs2,
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output pcpi_wr,
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output [31:0] pcpi_rd,
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output pcpi_wait,
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output pcpi_ready
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);
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reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
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wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
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wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
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wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
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wire instr_rs2_signed = |{instr_mulh};
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reg active1, active2, shift_out;
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reg [63:0] rs1, rs2, rd;
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always @* begin
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instr_mul = 0;
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instr_mulh = 0;
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instr_mulhsu = 0;
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instr_mulhu = 0;
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if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
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case (pcpi_insn[14:12])
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3'b000: instr_mul = 1;
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3'b001: instr_mulh = 1;
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3'b010: instr_mulhsu = 1;
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3'b011: instr_mulhu = 1;
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endcase
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end
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end
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always @(posedge clk) begin
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rd <= rs1 * rs2;
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end
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always @(posedge clk) begin
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if (instr_any_mul && !active1 && !active2) begin
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if (instr_rs1_signed)
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rs1 <= $signed(pcpi_rs1);
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else
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rs1 <= $unsigned(pcpi_rs1);
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if (instr_rs2_signed)
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rs2 <= $signed(pcpi_rs2);
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else
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rs2 <= $unsigned(pcpi_rs2);
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active1 <= 1;
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end else begin
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active1 <= 0;
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end
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active2 <= active1;
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shift_out <= instr_any_mulh;
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end
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assign pcpi_wr = active2;
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assign pcpi_wait = 0;
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assign pcpi_ready = active2;
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assign pcpi_rd = shift_out ? rd >> 32 : rd;
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endmodule
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/***************************************************************
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* picorv32_pcpi_div
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@ -1959,6 +2039,7 @@ module picorv32_axi #(
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_FAST_MUL = 0,
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parameter [ 0:0] ENABLE_DIV = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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@ -2066,6 +2147,7 @@ module picorv32_axi #(
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_MUL (ENABLE_MUL ),
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.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
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.ENABLE_DIV (ENABLE_DIV ),
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.ENABLE_IRQ (ENABLE_IRQ ),
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.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
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