mirror of https://github.com/YosysHQ/picorv32.git
Added hex8tohex32.py script to cxxdemo
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c59b0043c4
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@ -1,6 +1,7 @@
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firmware.d
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firmware.elf
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firmware.hex
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firmware32.hex
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firmware.o
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syscalls.o
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testbench.exe
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@ -6,17 +6,18 @@ CCFLAGS = -MD -Os -Wall -std=c++11
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LDFLAGS = -Wl,--gc-sections
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LDLIBS = -lstdc++
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test: testbench.exe firmware.hex
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test: testbench.exe firmware32.hex
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vvp -N testbench.exe
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testbench.exe: testbench.v ../../picorv32.v
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iverilog -o testbench.exe testbench.v ../../picorv32.v
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chmod -x testbench.exe
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firmware.hex: firmware.elf start.elf
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firmware32.hex: firmware.elf start.elf hex8tohex32.py
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riscv32-unknown-elf-objcopy -O verilog start.elf start.tmp
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riscv32-unknown-elf-objcopy -O verilog firmware.elf firmware.tmp
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cat start.tmp firmware.tmp > firmware.hex
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python3 hex8tohex32.py firmware.hex > firmware32.hex
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rm -f start.tmp firmware.tmp
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firmware.elf: firmware.o syscalls.o
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@ -29,7 +30,7 @@ start.elf: start.S start.ld
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clean:
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rm -f *.o *.d *.tmp start.elf
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rm -f firmware.elf firmware.hex
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rm -f firmware.elf firmware.hex firmware32.hex
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rm -f testbench.exe testbench.vcd
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-include *.d
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@ -0,0 +1,35 @@
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#!/usr/bin/env python3
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import fileinput
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import itertools
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ptr = 0
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data = []
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def write_data():
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if len(data) != 0:
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print("@%08x" % (ptr >> 2))
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while len(data) % 4 != 0:
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data.append(0)
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for word_bytes in zip(*([iter(data)]*4)):
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print("".join(["%02x" % b for b in reversed(word_bytes)]))
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for line in fileinput.input():
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if line.startswith("@"):
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addr = int(line[1:], 16)
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if addr > ptr+4:
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write_data()
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ptr = addr
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data = []
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while ptr % 4 != 0:
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data.append(0)
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ptr -= 1
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else:
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while ptr < addr:
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data.append(0)
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ptr += 1
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else:
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data += [int(tok, 16) for tok in line.split()]
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write_data()
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@ -1,6 +1,7 @@
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`timescale 1 ns / 1 ps
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`undef VERBOSE_MEM
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`undef WRITE_VCD
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`undef MEM8BIT
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module testbench;
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reg clk = 1;
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@ -36,8 +37,13 @@ module testbench;
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);
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localparam MEM_SIZE = 4*1024*1024;
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`ifdef MEM8BIT
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reg [7:0] memory [0:MEM_SIZE-1];
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initial $readmemh("firmware.hex", memory);
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`else
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reg [31:0] memory [0:MEM_SIZE/4-1];
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initial $readmemh("firmware32.hex", memory);
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`endif
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always @(posedge clk) begin
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mem_ready <= 0;
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@ -46,6 +52,7 @@ module testbench;
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mem_rdata <= 'bx;
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case (1)
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mem_addr < MEM_SIZE: begin
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`ifdef MEM8BIT
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if (|mem_wstrb) begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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@ -54,6 +61,16 @@ module testbench;
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end else begin
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mem_rdata <= {memory[mem_addr+3], memory[mem_addr+2], memory[mem_addr+1], memory[mem_addr]};
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end
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`else
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if (|mem_wstrb) begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end else begin
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mem_rdata <= memory[mem_addr >> 2];
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end
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`endif
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end
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mem_addr == 32'h 1000_0000: begin
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$write("%c", mem_wdata[7:0]);
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