mirror of https://github.com/YosysHQ/picorv32.git
Being more aggressive with parallel cases
This commit is contained in:
Clifford Wolf
parent
c10125eb5c
commit
ab503d5756
326
picorv32.v
326
picorv32.v
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@ -639,26 +639,29 @@ module picorv32 #(
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current_pc = reg_next_pc;
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current_pc = reg_next_pc;
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if (latched_branch) begin
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(* parallel_case *)
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current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc;
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case (1'b1)
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
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latched_branch: begin
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cpuregs[latched_rd] <= reg_pc + 4;
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current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc;
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end else
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`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
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if (latched_store) begin
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cpuregs[latched_rd] <= reg_pc + 4;
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`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);)
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end
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cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out;
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latched_store && !latched_branch: begin
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end else
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`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);)
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if (ENABLE_IRQ && irq_state[0]) begin
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cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out;
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cpuregs[latched_rd] <= current_pc;
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end
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current_pc = PROGADDR_IRQ;
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ENABLE_IRQ && irq_state[0]: begin
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irq_active <= 1;
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cpuregs[latched_rd] <= current_pc;
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mem_do_rinst <= 1;
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current_pc = PROGADDR_IRQ;
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end else
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irq_active <= 1;
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if (ENABLE_IRQ && irq_state[1]) begin
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mem_do_rinst <= 1;
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eoi <= irq_pending & ~irq_mask;
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end
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cpuregs[latched_rd] <= irq_pending & ~irq_mask;
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ENABLE_IRQ && irq_state[1]: begin
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next_irq_pending = next_irq_pending & irq_mask;
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eoi <= irq_pending & ~irq_mask;
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end
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cpuregs[latched_rd] <= irq_pending & ~irq_mask;
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next_irq_pending = next_irq_pending & irq_mask;
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end
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endcase
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reg_pc <= current_pc;
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reg_pc <= current_pc;
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reg_next_pc <= current_pc;
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reg_next_pc <= current_pc;
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@ -711,153 +714,178 @@ module picorv32 #(
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reg_op1 <= 'bx;
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reg_op1 <= 'bx;
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reg_op2 <= 'bx;
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reg_op2 <= 'bx;
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`debug($display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");)
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`debug($display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");)
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if ((CATCH_ILLINSN || WITH_PCPI) && instr_trap) begin
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if (WITH_PCPI) begin
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(* parallel_case *)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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case (1'b1)
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if (ENABLE_REGS_DUALPORT) begin
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(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
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pcpi_valid <= 1;
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if (WITH_PCPI) begin
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (ENABLE_REGS_DUALPORT) begin
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if (pcpi_int_ready) begin
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pcpi_valid <= 1;
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mem_do_rinst <= 1;
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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pcpi_valid <= 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_out <= pcpi_int_rd;
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if (pcpi_int_ready) begin
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latched_store <= pcpi_int_wr;
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mem_do_rinst <= 1;
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cpu_state <= cpu_state_fetch;
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pcpi_valid <= 0;
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end else
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reg_out <= pcpi_int_rd;
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if (CATCH_ILLINSN && pcpi_timeout) begin
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latched_store <= pcpi_int_wr;
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_fetch;
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end else
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end else
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cpu_state <= cpu_state_trap;
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if (CATCH_ILLINSN && pcpi_timeout) begin
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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end else
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cpu_state <= cpu_state_trap;
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end
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end else begin
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cpu_state <= cpu_state_ld_rs2;
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end
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end
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end else begin
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end else begin
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cpu_state <= cpu_state_ld_rs2;
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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end else
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cpu_state <= cpu_state_trap;
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end
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end
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end else begin
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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end else
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cpu_state <= cpu_state_trap;
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end
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end
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end else
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ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
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if (is_rdcycle_rdcycleh_rdinstr_rdinstrh) begin
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(* parallel_case, full_case *)
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(* parallel_case, full_case *)
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case (1'b1)
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case (1'b1)
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instr_rdcycle:
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instr_rdcycle:
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reg_out <= count_cycle[31:0];
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reg_out <= count_cycle[31:0];
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instr_rdcycleh:
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instr_rdcycleh:
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reg_out <= count_cycle[63:32];
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reg_out <= count_cycle[63:32];
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instr_rdinstr:
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instr_rdinstr:
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reg_out <= count_instr[31:0];
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reg_out <= count_instr[31:0];
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instr_rdinstrh:
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instr_rdinstrh:
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reg_out <= count_instr[63:32];
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reg_out <= count_instr[63:32];
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endcase
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endcase
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latched_store <= 1;
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latched_store <= 1;
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_fetch;
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end
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end else
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is_lui_auipc_jal: begin
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if (is_lui_auipc_jal) begin
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reg_op1 <= instr_lui ? 0 : reg_pc;
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reg_op1 <= instr_lui ? 0 : reg_pc;
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reg_op2 <= decoded_imm;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end else
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if (ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq) begin
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reg_out <= cpuregs[decoded_rs1];
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latched_store <= 1;
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq) begin
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reg_out <= cpuregs[decoded_rs1];
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latched_rd <= latched_rd | irqregs_offset;
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latched_store <= 1;
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && instr_retirq) begin
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eoi <= 0;
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irq_active <= 0;
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latched_branch <= 1;
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latched_store <= 1;
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reg_out <= cpuregs[decoded_rs1];
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && instr_maskirq) begin
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latched_store <= 1;
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reg_out <= irq_mask;
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irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ;
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer) begin
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latched_store <= 1;
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reg_out <= timer;
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timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpu_state <= cpu_state_fetch;
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end else begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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if (is_lb_lh_lw_lbu_lhu) begin
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cpu_state <= cpu_state_ldmem;
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mem_do_rinst <= 1;
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end else if (is_slli_srli_srai) begin
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reg_sh <= decoded_rs2;
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cpu_state <= cpu_state_shift;
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end else if (is_jalr_addi_slti_sltiu_xori_ori_andi) begin
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reg_op2 <= decoded_imm;
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reg_op2 <= decoded_imm;
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mem_do_rinst <= mem_do_prefetch;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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cpu_state <= cpu_state_exec;
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end else if (ENABLE_REGS_DUALPORT) begin
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end
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_out <= cpuregs[decoded_rs1];
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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latched_store <= 1;
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if (is_sb_sh_sw) begin
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_stmem;
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end
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mem_do_rinst <= 1;
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ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
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end else if (is_sll_srl_sra) begin
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reg_out <= cpuregs[decoded_rs1];
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cpu_state <= cpu_state_shift;
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latched_rd <= latched_rd | irqregs_offset;
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end else begin
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latched_store <= 1;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_exec;
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end
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end
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ENABLE_IRQ && instr_retirq: begin
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end else
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eoi <= 0;
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cpu_state <= cpu_state_ld_rs2;
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irq_active <= 0;
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end
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latched_branch <= 1;
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latched_store <= 1;
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reg_out <= cpuregs[decoded_rs1];
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cpu_state <= cpu_state_fetch;
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end
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ENABLE_IRQ && instr_maskirq: begin
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latched_store <= 1;
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reg_out <= irq_mask;
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irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ;
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cpu_state <= cpu_state_fetch;
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end
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ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
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latched_store <= 1;
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reg_out <= timer;
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timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpu_state <= cpu_state_fetch;
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end
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is_lb_lh_lw_lbu_lhu: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpu_state <= cpu_state_ldmem;
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mem_do_rinst <= 1;
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end
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is_slli_srli_srai: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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reg_sh <= decoded_rs2;
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cpu_state <= cpu_state_shift;
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end
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is_jalr_addi_slti_sltiu_xori_ori_andi: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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reg_op2 <= decoded_imm;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end
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default: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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if (ENABLE_REGS_DUALPORT) begin
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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(* parallel_case *)
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case (1'b1)
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is_sb_sh_sw: begin
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cpu_state <= cpu_state_stmem;
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mem_do_rinst <= 1;
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end
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is_sll_srl_sra: begin
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cpu_state <= cpu_state_shift;
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end
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default: begin
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end
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endcase
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end else
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cpu_state <= cpu_state_ld_rs2;
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end
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endcase
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end
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end
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cpu_state_ld_rs2: begin
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cpu_state_ld_rs2: begin
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);)
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (WITH_PCPI && instr_trap) begin
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pcpi_valid <= 1;
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(* parallel_case *)
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if (pcpi_int_ready) begin
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case (1'b1)
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mem_do_rinst <= 1;
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WITH_PCPI && instr_trap: begin
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pcpi_valid <= 0;
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pcpi_valid <= 1;
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reg_out <= pcpi_int_rd;
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if (pcpi_int_ready) begin
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latched_store <= pcpi_int_wr;
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mem_do_rinst <= 1;
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cpu_state <= cpu_state_fetch;
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pcpi_valid <= 0;
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end else
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reg_out <= pcpi_int_rd;
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if (CATCH_ILLINSN && pcpi_timeout) begin
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latched_store <= pcpi_int_wr;
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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cpu_state <= cpu_state_fetch;
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end else
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end else
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cpu_state <= cpu_state_trap;
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if (CATCH_ILLINSN && pcpi_timeout) begin
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`debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
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next_irq_pending[irq_sbreak] = 1;
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cpu_state <= cpu_state_fetch;
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end else
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cpu_state <= cpu_state_trap;
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end
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end
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end
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end else
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is_sb_sh_sw: begin
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if (is_sb_sh_sw) begin
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cpu_state <= cpu_state_stmem;
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cpu_state <= cpu_state_stmem;
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mem_do_rinst <= 1;
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mem_do_rinst <= 1;
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end
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end else if (is_sll_srl_sra) begin
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is_sll_srl_sra: begin
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cpu_state <= cpu_state_shift;
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cpu_state <= cpu_state_shift;
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end else begin
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end
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mem_do_rinst <= mem_do_prefetch;
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default: begin
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cpu_state <= cpu_state_exec;
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mem_do_rinst <= mem_do_prefetch;
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end
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cpu_state <= cpu_state_exec;
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end
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endcase
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end
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end
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cpu_state_exec: begin
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cpu_state_exec: begin
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Reference in New Issue