mirror of https://github.com/YosysHQ/picorv32.git
Remove generic PicoSoC testbench
This commit is contained in:
parent
8b5f2aeff3
commit
ae0e5a6c94
|
@ -1,5 +1,3 @@
|
|||
/testbench.vcd
|
||||
/testbench.vvp
|
||||
/spiflash_tb.vcd
|
||||
/spiflash_tb.vvp
|
||||
/firmware.elf
|
||||
|
@ -13,3 +11,4 @@
|
|||
/hx8kdemo_syn.v
|
||||
/hx8kdemo_syn_tb.vvp
|
||||
/hx8kdemo_tb.vvp
|
||||
/testbench.vcd
|
||||
|
|
|
@ -1,27 +1,6 @@
|
|||
|
||||
# ---- Generic Testbenches ----
|
||||
|
||||
testbench: testbench.vvp firmware.hex
|
||||
vvp -N $<
|
||||
|
||||
testbench.vvp: spiflash.v spimemio.v simpleuart.v testbench.v picosoc.v ../picorv32.v
|
||||
iverilog -s testbench -o $@ $^
|
||||
|
||||
spiflash_tb: spiflash_tb.vvp firmware.hex
|
||||
vvp -N $<
|
||||
|
||||
spiflash_tb.vvp: spiflash.v spiflash_tb.v
|
||||
iverilog -s testbench -o $@ $^
|
||||
|
||||
# ---- iCE40 HX8K Breakout Board ----
|
||||
|
||||
hx8kprog: hx8kdemo.bin firmware.bin
|
||||
iceprog hx8kdemo.bin
|
||||
iceprog -o 1M firmware.bin
|
||||
|
||||
hx8kprog_fw: firmware.bin
|
||||
iceprog -o 1M firmware.bin
|
||||
|
||||
hx8ksim: hx8kdemo_tb.vvp firmware.hex
|
||||
vvp -N $<
|
||||
|
||||
|
@ -47,6 +26,13 @@ hx8kdemo.bin: hx8kdemo.asc
|
|||
icetime -d hx8k -c 12 -mtr hx8kdemo.rpt hx8kdemo.asc
|
||||
icepack hx8kdemo.asc hx8kdemo.bin
|
||||
|
||||
hx8kprog: hx8kdemo.bin firmware.bin
|
||||
iceprog hx8kdemo.bin
|
||||
iceprog -o 1M firmware.bin
|
||||
|
||||
hx8kprog_fw: firmware.bin
|
||||
iceprog -o 1M firmware.bin
|
||||
|
||||
# ---- Example Firmware ----
|
||||
|
||||
firmware.elf: sections.lds start.s firmware.c
|
||||
|
@ -58,6 +44,14 @@ firmware.hex: firmware.elf
|
|||
firmware.bin: firmware.elf
|
||||
riscv32-unknown-elf-objcopy -O binary firmware.elf /dev/stdout | tail -c +1048577 > firmware.bin
|
||||
|
||||
# ---- Testbench for SPI Flash Model ----
|
||||
|
||||
spiflash_tb: spiflash_tb.vvp firmware.hex
|
||||
vvp -N $<
|
||||
|
||||
spiflash_tb.vvp: spiflash.v spiflash_tb.v
|
||||
iverilog -s testbench -o $@ $^
|
||||
|
||||
# ---- Clean ----
|
||||
|
||||
clean:
|
||||
|
@ -66,5 +60,5 @@ clean:
|
|||
rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
|
||||
rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
|
||||
|
||||
.PHONY: testbench spiflash_tb hx8kprog hx8kprog_fw hx8ksim hx8ksynsim clean
|
||||
.PHONY: spiflash_tb hx8kprog hx8kprog_fw hx8ksim hx8ksynsim clean
|
||||
|
||||
|
|
|
@ -1,150 +0,0 @@
|
|||
/*
|
||||
* PicoSoC - A simple example SoC using PicoRV32
|
||||
*
|
||||
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module testbench;
|
||||
reg clk;
|
||||
always #5 clk = (clk === 1'b0);
|
||||
|
||||
reg resetn = 0;
|
||||
integer cycles = 0;
|
||||
|
||||
always @(posedge clk)
|
||||
cycles <= cycles + 1;
|
||||
|
||||
initial begin
|
||||
$dumpfile("testbench.vcd");
|
||||
$dumpvars(0, testbench);
|
||||
|
||||
repeat (100) @(posedge clk);
|
||||
resetn <= 1;
|
||||
|
||||
repeat (100000) @(posedge clk);
|
||||
|
||||
$display("");
|
||||
$display("[TIMEOUT]");
|
||||
$stop;
|
||||
end
|
||||
|
||||
wire flash_csb;
|
||||
wire flash_clk;
|
||||
|
||||
wire flash_io0;
|
||||
wire flash_io1;
|
||||
wire flash_io2;
|
||||
wire flash_io3;
|
||||
|
||||
wire flash_io0_oe;
|
||||
wire flash_io1_oe;
|
||||
wire flash_io2_oe;
|
||||
wire flash_io3_oe;
|
||||
|
||||
wire flash_io0_do;
|
||||
wire flash_io1_do;
|
||||
wire flash_io2_do;
|
||||
wire flash_io3_do;
|
||||
|
||||
wire flash_io0_di = flash_io0;
|
||||
wire flash_io1_di = flash_io1;
|
||||
wire flash_io2_di = flash_io2;
|
||||
wire flash_io3_di = flash_io3;
|
||||
|
||||
assign flash_io0 = flash_io0_oe ? flash_io0_do : 1'bz;
|
||||
assign flash_io1 = flash_io1_oe ? flash_io1_do : 1'bz;
|
||||
assign flash_io2 = flash_io2_oe ? flash_io2_do : 1'bz;
|
||||
assign flash_io3 = flash_io3_oe ? flash_io3_do : 1'bz;
|
||||
|
||||
wire iomem_valid;
|
||||
reg iomem_ready;
|
||||
wire [3:0] iomem_wstrb;
|
||||
wire [31:0] iomem_addr;
|
||||
wire [31:0] iomem_wdata;
|
||||
reg [31:0] iomem_rdata;
|
||||
|
||||
wire ser_tx_rx;
|
||||
|
||||
reg [31:0] gpio;
|
||||
|
||||
always @(posedge clk) begin
|
||||
iomem_ready <= 0;
|
||||
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
|
||||
iomem_ready <= 1;
|
||||
iomem_rdata <= gpio;
|
||||
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
|
||||
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
|
||||
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
|
||||
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
|
||||
end
|
||||
end
|
||||
|
||||
always @(gpio) begin
|
||||
$write("<GPIO:%02x>", gpio[7:0]);
|
||||
if (gpio == 63) begin
|
||||
$display("[OK]");
|
||||
$display("Finished after %0d cycles.", cycles);
|
||||
$finish;
|
||||
end
|
||||
if (gpio % 8 == 7) begin
|
||||
$display("");
|
||||
end
|
||||
end
|
||||
|
||||
picosoc uut (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
|
||||
.ser_tx (ser_tx_rx ),
|
||||
.ser_rx (ser_tx_rx ),
|
||||
|
||||
.flash_csb (flash_csb ),
|
||||
.flash_clk (flash_clk ),
|
||||
|
||||
.flash_io0_oe (flash_io0_oe),
|
||||
.flash_io1_oe (flash_io1_oe),
|
||||
.flash_io2_oe (flash_io2_oe),
|
||||
.flash_io3_oe (flash_io3_oe),
|
||||
|
||||
.flash_io0_do (flash_io0_do),
|
||||
.flash_io1_do (flash_io1_do),
|
||||
.flash_io2_do (flash_io2_do),
|
||||
.flash_io3_do (flash_io3_do),
|
||||
|
||||
.flash_io0_di (flash_io0_di),
|
||||
.flash_io1_di (flash_io1_di),
|
||||
.flash_io2_di (flash_io2_di),
|
||||
.flash_io3_di (flash_io3_di),
|
||||
|
||||
.iomem_valid (iomem_valid ),
|
||||
.iomem_ready (iomem_ready ),
|
||||
.iomem_wstrb (iomem_wstrb ),
|
||||
.iomem_addr (iomem_addr ),
|
||||
.iomem_wdata (iomem_wdata ),
|
||||
.iomem_rdata (iomem_rdata )
|
||||
);
|
||||
|
||||
spiflash spiflash (
|
||||
.csb(flash_csb),
|
||||
.clk(flash_clk),
|
||||
.io0(flash_io0),
|
||||
.io1(flash_io1),
|
||||
.io2(flash_io2),
|
||||
.io3(flash_io3)
|
||||
);
|
||||
endmodule
|
Loading…
Reference in New Issue