Updated eval data

README.md

@@ -533,7 +533,7 @@ The following evaluations have been performed with Vivado 2015.1.
 
 #### Timing on Xilinx 7-Series FPGAs
 
-The `picorv32_axi` module in its default configuration has been placed and
+The `picorv32_axi` module with enabled `TWO_CYCLE_COMPARE` has been placed and
 routed for Xilinx Artix-7T (xc7a15t-fgg484), Xilinx Kintex-7T (xc7k70t-fbg676),
 and Xilinx Virtex-7T (xc7v585t-ffg1761) devices in all speed grades. A binary
 search is used to find the lowest clock period for which the design meets
@@ -543,15 +543,15 @@ See `make table.txt` in [scripts/vivado/](scripts/vivado/).
 
 | Device               | Speedgrade | Clock Period (Freq.) |
 |:-------------------- |:----------:| --------------------:|
-| Xilinx Artix-7T      | -1         |     4.8 ns (208 MHz) |
-| Xilinx Artix-7T      | -2         |     3.9 ns (256 MHz) |
+| Xilinx Artix-7T      | -1         |     4.6 ns (217 MHz) |
+| Xilinx Artix-7T      | -2         |     4.0 ns (250 MHz) |
 | Xilinx Artix-7T      | -3         |     3.4 ns (294 MHz) |
-| Xilinx Kintex-7T     | -1         |     3.2 ns (312 MHz) |
-| Xilinx Kintex-7T     | -2         |     2.5 ns (400 MHz) |
-| Xilinx Kintex-7T     | -3         |     2.6 ns (384 MHz) |
+| Xilinx Kintex-7T     | -1         |     3.0 ns (333 MHz) |
+| Xilinx Kintex-7T     | -2         |     2.7 ns (370 MHz) |
+| Xilinx Kintex-7T     | -3         |     2.5 ns (400 MHz) |
 | Xilinx Virtex-7T     | -1         |     3.0 ns (333 MHz) |
-| Xilinx Virtex-7T     | -2         |     2.7 ns (370 MHz) |
-| Xilinx Virtex-7T     | -3         |     2.3 ns (434 MHz) |
+| Xilinx Virtex-7T     | -2         |     2.5 ns (400 MHz) |
+| Xilinx Virtex-7T     | -3         |     2.2 ns (454 MHz) |
 
 #### Utilization on Xilinx 7-Series FPGAs
 
@@ -572,6 +572,6 @@ See `make area` in [scripts/vivado/](scripts/vivado/).
 | Core Variant       | Slice LUTs | LUTs as Memory | Slice Registers |
 |:------------------ | ----------:| --------------:| ---------------:|
 | PicoRV32 (small)   |        775 |             48 |             422 |
-| PicoRV32 (regular) |        963 |             48 |             564 |
-| PicoRV32 (large)   |       1800 |             88 |            1002 |
+| PicoRV32 (regular) |        960 |             48 |             564 |
+| PicoRV32 (large)   |       1684 |             88 |            1002 |
 

scripts/vivado/tabtest.sh

@@ -51,13 +51,16 @@ synth_case() {
 	mv test_${1}.log test_${1}.txt
 }
 
-while [ $step -gt 0 ]; do
+countdown=2
+while [ $countdown -gt 0 ]; do
 	synth_case $speed
 
 	if grep -q '^Slack.*(VIOLATED)' test_${speed}.txt; then
+		echo "        tab_${ip}_${dev}_${grade}/test_${speed} VIOLATED"
 		[ $speed -eq 38 ] || step=$((step / 2))
 		speed=$((speed + step))
 	elif grep -q '^Slack.*(MET)' test_${speed}.txt; then
+		echo "        tab_${ip}_${dev}_${grade}/test_${speed} MET"
 		[ $speed -lt $best_speed ] && best_speed=$speed
 		step=$((step / 2))
 		speed=$((speed - step))
@@ -65,7 +68,16 @@ while [ $step -gt 0 ]; do
 		echo "ERROR: No slack line found in $PWD/test_${speed}.txt!"
 		exit 1
 	fi
+
+	if [ $step -eq 0 ]; then
+		countdown=$((countdown - 1))
+		speed=$((best_speed - 2))
+		step=1
+	fi
 done
 
+echo "-----------------------"
+echo "Best speed for tab_${ip}_${dev}_${grade}: $best_speed"
+echo "-----------------------"
 echo $best_speed > results.txt
 

scripts/vivado/tabtest.v

@@ -72,7 +72,9 @@ module top (
 	delay4 #(32) delay_irq             (clk, io_irq            ,    irq            );
 	delay4 #(32) delay_eoi             (clk,    eoi            , io_eoi            );
 
-	picorv32_axi core (
+	picorv32_axi #(
+		.TWO_CYCLE_COMPARE(1)
+	) cpu (
 		.clk            (clk            ),
 		.resetn         (resetn         ),
 		.trap           (trap           ),