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Fixed "make test_synth"

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This commit is contained in:
Clifford Wolf 2016-12-15 12:48:57 +01:00
parent 72d6f6f72d
commit ca5702c75f
1 changed files with 2 additions and 1 deletions
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3
scripts/yosys/synth_sim.ys
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@ -1,7 +1,8 @@
# yosys synthesis script for post-synthesis simulation (make test_synth)
read_verilog picorv32.v
chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
-set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
hierarchy -top picorv32_axi
synth
write_verilog synth.v