Update big endian instruction encoding

Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>

README.md

@@ -327,13 +327,9 @@ i.e. the most significant bits at the lowest address.
 
 #### BIG_ENDIAN_INSNS (default 0)
 
-Set this to 1 to enable big endian instruction streams, i.e. the parcel in
-`mem_rdata[31:16]` logically precedes the one in `mem_rdata[15:0]`,
-and provides lower numbered bits in case the parcels are part of the same
-instruction.
-This is how the official RISC-V documents say instructions should be encoded
-on big endian, but note that current toolchains do not support generating
-code in this format.
+Set this to 1 to enable byteswapping of the instruction stream.
+This is required on big endian because instructions are stored in little
+endian byteorder.
 
 
 Cycles per Instruction Performance

picorv32.v

@@ -385,7 +385,7 @@ module picorv32 #(
 	assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
 
 	generate if (BIG_ENDIAN_INSNS) begin
-		assign mem_rdata_insn = { mem_rdata[15:0], mem_rdata[31:16] };
+		assign mem_rdata_insn = { mem_rdata[7:0], mem_rdata[15:8], mem_rdata[23:16], mem_rdata[31:24] };
 	end else begin
 		assign mem_rdata_insn = mem_rdata;
 	end endgenerate