mirror of https://github.com/YosysHQ/picorv32.git
Update rvfi_order according to current rvfi spec
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@ -109,7 +109,7 @@ module picorv32 #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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output reg rvfi_valid,
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output reg rvfi_valid,
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output reg [ 7:0] rvfi_order,
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output reg [63:0] rvfi_order,
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output reg [31:0] rvfi_insn,
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output reg [31:0] rvfi_insn,
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output reg rvfi_trap,
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output reg rvfi_trap,
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output reg rvfi_halt,
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output reg rvfi_halt,
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@ -1905,7 +1905,7 @@ module picorv32 #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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always @(posedge clk) begin
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always @(posedge clk) begin
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rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
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rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
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rvfi_order <= 0;
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rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
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rvfi_insn <= dbg_insn_opcode;
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rvfi_insn <= dbg_insn_opcode;
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rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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@ -2392,7 +2392,7 @@ module picorv32_axi #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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output rvfi_valid,
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output rvfi_valid,
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output [ 7:0] rvfi_order,
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output [63:0] rvfi_order,
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output [31:0] rvfi_insn,
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output [31:0] rvfi_insn,
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output rvfi_trap,
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output rvfi_trap,
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output [ 4:0] rvfi_rs1_addr,
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output [ 4:0] rvfi_rs1_addr,
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@ -2674,7 +2674,7 @@ module picorv32_wb #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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output rvfi_valid,
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output rvfi_valid,
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output [ 7:0] rvfi_order,
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output [63:0] rvfi_order,
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output [31:0] rvfi_insn,
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output [31:0] rvfi_insn,
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output rvfi_trap,
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output rvfi_trap,
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output [ 4:0] rvfi_rs1_addr,
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output [ 4:0] rvfi_rs1_addr,
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