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Update README.md

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Clifford Wolf 2019-08-09 09:23:17 +02:00 committed by GitHub
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@ -92,7 +92,7 @@ This Verilog file contains the following Verilog modules:
| `picorv32_axi` | The version of the CPU with AXI4-Lite interface | | `picorv32_axi` | The version of the CPU with AXI4-Lite interface |
| `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite | | `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite |
| `picorv32_wb` | The version of the CPU with Wishbone Master interface | | `picorv32_wb` | The version of the CPU with Wishbone Master interface |
| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions | | `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU\|U]]` instructions |
| `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier | | `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier |
| `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions | | `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions |