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Fix spiflash_tb 

Update expected two first Flash words to reflect changes in start.s

Add dummy SPI cycles to account for latency
This commit is contained in:
Olof Kindgren 2018-05-11 22:56:52 +02:00
parent 8b32bc5bd6
commit d26e505251
1 changed files with 6 additions and 6 deletions
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12
picosoc/spiflash_tb.v
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@ -53,8 +53,8 @@ module testbench;
);
localparam [23:0] offset = 24'h100000;
localparam [31:0] word0 = 32'h 01300293;
localparam [31:0] word1 = 32'h 00502223;
localparam [31:0] word0 = 32'h 00000093;
localparam [31:0] word1 = 32'h 00000193;
reg [7:0] rdata;
integer errcount = 0;
@ -291,7 +291,7 @@ module testbench;
xfer_qspi_wr(offset[15:8]);
xfer_qspi_wr(offset[7:0]);
xfer_qspi_wr(8'h a5);
xfer_dummy;
repeat (8) xfer_dummy;
xfer_qspi_rd; expect(word0[7:0]);
xfer_qspi_rd; expect(word0[15:8]);
xfer_qspi_rd; expect(word0[23:16]);
@ -308,7 +308,7 @@ module testbench;
xfer_qspi_wr(offset[15:8]);
xfer_qspi_wr(offset[7:0]);
xfer_qspi_wr(8'h ff);
xfer_dummy;
repeat (8) xfer_dummy;
xfer_qspi_rd; expect(word0[7:0]);
xfer_qspi_rd; expect(word0[15:8]);
xfer_qspi_rd; expect(word0[23:16]);
@ -326,7 +326,7 @@ module testbench;
xfer_qspi_ddr_wr(offset[15:8]);
xfer_qspi_ddr_wr(offset[7:0]);
xfer_qspi_ddr_wr(8'h a5);
xfer_dummy;
repeat (8) xfer_dummy;
xfer_qspi_ddr_rd; expect(word0[7:0]);
xfer_qspi_ddr_rd; expect(word0[15:8]);
xfer_qspi_ddr_rd; expect(word0[23:16]);
@ -343,7 +343,7 @@ module testbench;
xfer_qspi_ddr_wr(offset[15:8]);
xfer_qspi_ddr_wr(offset[7:0]);
xfer_qspi_ddr_wr(8'h ff);
xfer_dummy;
repeat (8) xfer_dummy;
xfer_qspi_ddr_rd; expect(word0[7:0]);
xfer_qspi_ddr_rd; expect(word0[15:8]);
xfer_qspi_ddr_rd; expect(word0[23:16]);