mirror of https://github.com/YosysHQ/picorv32.git
Added "make table.txt" vivado scripts
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README.md
20
README.md
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@ -311,6 +311,26 @@ makes it easy to install them side-by-side with the regular riscv-tools, which
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are using the name prefix `riscv64-unknown-elf-` by default.
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are using the name prefix `riscv64-unknown-elf-` by default.
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Evaluation: Timing on Xilinx 7-Series FPGAs
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-------------------------------------------
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The following table lists the maximum clock speeds that PicoRV32 can run at on
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Xilinx 7-Series FPGAs. This are the values reported by Vivado 2015.1 post
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place&route static timing analysis (report_timing).
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| Device | Speedgrade | Clock Period (Freq.) |
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|:-------------------- |:----------:| --------------------:|
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| Xilinx Artix-7T | -1 | 5.1 ns (196 MHz) |
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| Xilinx Artix-7T | -2 | 4.1 ns (243 MHz) |
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| Xilinx Artix-7T | -3 | 3.6 ns (277 MHz) |
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| Xilinx Kintex-7T | -1 | 3.3 ns (303 MHz) |
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| Xilinx Kintex-7T | -2 | 2.6 ns (384 MHz) |
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| Xilinx Kintex-7T | -3 | 2.5 ns (400 MHz) |
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| Xilinx Virtex-7T | -1 | 3.1 ns (322 MHz) |
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| Xilinx Virtex-7T | -2 | 2.6 ns (384 MHz) |
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| Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) |
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Todos:
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Todos:
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------
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------
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@ -2,3 +2,4 @@ synth_*.log
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synth_*.mmi
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synth_*.mmi
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synth_*.bit
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synth_*.bit
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synth_*.v
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synth_*.v
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tab_*/
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@ -1,5 +1,5 @@
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VIVADO = /opt/Xilinx/Vivado/2014.4/bin/vivado
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export VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado
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help:
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help:
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@echo "Usage: make {synth_speed|synth_area|synth_soc}"
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@echo "Usage: make {synth_speed|synth_area|synth_soc}"
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@ -8,3 +8,13 @@ synth_%:
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$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
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$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
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rm -rf .Xil fsm_encoding.os synth_*.backup.log usage_statistics_webtalk.*
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rm -rf .Xil fsm_encoding.os synth_*.backup.log usage_statistics_webtalk.*
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tab_%/results.txt:
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bash tabtest.sh $@
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table.txt: tab_small_xc7a_1/results.txt tab_small_xc7a_2/results.txt tab_small_xc7a_3/results.txt
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table.txt: tab_small_xc7k_1/results.txt tab_small_xc7k_2/results.txt tab_small_xc7k_3/results.txt
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table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_xc7v_3/results.txt
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table.txt:
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bash table.sh > table.txt
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@ -0,0 +1,17 @@
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#!/bin/bash
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dashes="----------------------------------------------------------------"
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printf '| %-20s | %-10s | %-20s |\n' "Device" "Speedgrade" "Clock Period (Freq.)"
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printf '|:%.20s |:%.10s:| %.20s:|\n' $dashes $dashes $dashes
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for x in $( grep -H . tab_*/results.txt )
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do
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read _ size device grade _ speed < <( echo "$x" | tr _/: ' ' )
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case "$device" in
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xc7a) d="Xilinx Artix-7T" ;;
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xc7k) d="Xilinx Kintex-7T" ;;
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xc7v) d="Xilinx Virtex-7T" ;;
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esac
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speedtxt=$( printf '%s.%s ns (%d MHz)' ${speed%?} ${speed#?} $((10000 / speed)) )
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printf '| %-20s | %-10s | %20s |\n' "$d" "-$grade" "$speedtxt"
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done
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@ -0,0 +1,71 @@
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#!/bin/bash
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set -e
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read _ ip dev grade _ < <( echo $* | tr '_/' ' '; )
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# rm -rf tab_${ip}_${dev}_${grade}
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mkdir -p tab_${ip}_${dev}_${grade}
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cd tab_${ip}_${dev}_${grade}
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best_speed=99
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speed=30
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step=16
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synth_case() {
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if [ -f test_${1}.txt ]; then
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echo "Reusing cached tab_${ip}_${dev}_${grade}/test_${1}."
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return
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fi
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case "${dev}" in
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xc7a) xl_device="xc7a15t-fgg484-${grade}" ;;
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xc7k) xl_device="xc7k70t-fbg676-${grade}" ;;
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xc7v) xl_device="xc7v585t-ffg1761-${grade}" ;;
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esac
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cat > test_${1}.tcl <<- EOT
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read_verilog ../tabtest.v
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read_verilog ../../../picorv32.v
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read_xdc test_${1}.xdc
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synth_design -flatten_hierarchy full -part ${xl_device} -top top
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opt_design -sweep -remap
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place_design -directive Explore
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phys_opt_design -retime -rewire -critical_pin_opt -placement_opt -critical_cell_opt
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route_design -directive Explore
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place_design -post_place_opt
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phys_opt_design -retime
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route_design -directive NoTimingRelaxation
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report_utilization
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report_timing
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EOT
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cat > test_${1}.xdc <<- EOT
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create_clock -period ${speed%?}.${speed#?} [get_ports clk]
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EOT
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echo "Running tab_${ip}_${dev}_${grade}/test_${1}.."
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if ! $VIVADO -nojournal -log test_${1}.log -mode batch -source test_${1}.tcl > /dev/null 2>&1; then
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cat test_${1}.log
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exit 1
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fi
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mv test_${1}.log test_${1}.txt
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}
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while [ $step -gt 0 ]; do
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synth_case $speed
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if grep -q '^Slack.*(VIOLATED)' test_${speed}.txt; then
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[ $speed -eq 38 ] || step=$((step / 2))
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speed=$((speed + step))
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elif grep -q '^Slack.*(MET)' test_${speed}.txt; then
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[ $speed -lt $best_speed ] && best_speed=$speed
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step=$((step / 2))
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speed=$((speed - step))
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else
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echo "ERROR: No slack line found in $PWD/test_${speed}.txt!"
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exit 1
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fi
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done
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echo $best_speed > results.txt
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@ -0,0 +1,116 @@
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module top (
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input clk, io_resetn,
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output io_trap,
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output io_mem_axi_awvalid,
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input io_mem_axi_awready,
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output [31:0] io_mem_axi_awaddr,
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output [ 2:0] io_mem_axi_awprot,
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output io_mem_axi_wvalid,
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input io_mem_axi_wready,
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output [31:0] io_mem_axi_wdata,
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output [ 3:0] io_mem_axi_wstrb,
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input io_mem_axi_bvalid,
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output io_mem_axi_bready,
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output io_mem_axi_arvalid,
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input io_mem_axi_arready,
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output [31:0] io_mem_axi_araddr,
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output [ 2:0] io_mem_axi_arprot,
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input io_mem_axi_rvalid,
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output io_mem_axi_rready,
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input [31:0] io_mem_axi_rdata,
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input [31:0] io_irq,
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output [31:0] io_eoi
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);
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wire resetn;
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wire trap;
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wire mem_axi_awvalid;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [3:0] mem_axi_wstrb;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [2:0] mem_axi_arprot;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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wire [31:0] mem_axi_rdata;
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wire [31:0] irq;
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wire [31:0] eoi;
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delay4 #( 1) delay_resetn (clk, io_resetn , resetn );
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delay4 #( 1) delay_trap (clk, trap , io_trap );
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delay4 #( 1) delay_mem_axi_awvalid (clk, mem_axi_awvalid, io_mem_axi_awvalid);
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delay4 #( 1) delay_mem_axi_awready (clk, io_mem_axi_awready, mem_axi_awready);
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delay4 #(32) delay_mem_axi_awaddr (clk, mem_axi_awaddr , io_mem_axi_awaddr );
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delay4 #( 3) delay_mem_axi_awprot (clk, mem_axi_awprot , io_mem_axi_awprot );
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delay4 #( 1) delay_mem_axi_wvalid (clk, mem_axi_wvalid , io_mem_axi_wvalid );
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delay4 #( 1) delay_mem_axi_wready (clk, io_mem_axi_wready , mem_axi_wready );
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delay4 #(32) delay_mem_axi_wdata (clk, mem_axi_wdata , io_mem_axi_wdata );
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delay4 #( 4) delay_mem_axi_wstrb (clk, mem_axi_wstrb , io_mem_axi_wstrb );
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delay4 #( 1) delay_mem_axi_bvalid (clk, io_mem_axi_bvalid , mem_axi_bvalid );
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delay4 #( 1) delay_mem_axi_bready (clk, mem_axi_bready , io_mem_axi_bready );
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delay4 #( 1) delay_mem_axi_arvalid (clk, mem_axi_arvalid, io_mem_axi_arvalid);
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delay4 #( 1) delay_mem_axi_arready (clk, io_mem_axi_arready, mem_axi_arready);
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delay4 #(32) delay_mem_axi_araddr (clk, mem_axi_araddr , io_mem_axi_araddr );
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delay4 #( 3) delay_mem_axi_arprot (clk, mem_axi_arprot , io_mem_axi_arprot );
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delay4 #( 1) delay_mem_axi_rvalid (clk, io_mem_axi_rvalid , mem_axi_rvalid );
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delay4 #( 1) delay_mem_axi_rready (clk, mem_axi_rready , io_mem_axi_rready );
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delay4 #(32) delay_mem_axi_rdata (clk, io_mem_axi_rdata , mem_axi_rdata );
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delay4 #(32) delay_irq (clk, io_irq , irq );
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delay4 #(32) delay_eoi (clk, eoi , io_eoi );
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picorv32_axi core (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_axi_awvalid(mem_axi_awvalid),
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.mem_axi_awready(mem_axi_awready),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid(mem_axi_arvalid),
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.mem_axi_arready(mem_axi_arready),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.irq (irq ),
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.eoi (eoi )
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);
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endmodule
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module delay4 #(
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parameter WIDTH = 1
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) (
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input clk,
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input [WIDTH-1:0] in,
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output reg [WIDTH-1:0] out
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);
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reg [WIDTH-1:0] q1, q2, q3;
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always @(posedge clk) begin
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q1 <= in;
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q2 <= q1;
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q3 <= q2;
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out <= q3;
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end
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endmodule
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