mirror of https://github.com/YosysHQ/picorv32.git
More picorv32_pcpi_mul timing improvements
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picorv32.v
19
picorv32.v
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@ -1917,7 +1917,8 @@ module picorv32_pcpi_mul #(
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endmodule
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endmodule
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module picorv32_pcpi_fast_mul #(
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module picorv32_pcpi_fast_mul #(
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parameter EXTRA_FFS = 0
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parameter EXTRA_MUL_FFS = 0,
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parameter EXTRA_INSN_FFS = 0
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) (
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) (
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input clk, resetn,
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input clk, resetn,
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@ -1941,13 +1942,16 @@ module picorv32_pcpi_fast_mul #(
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reg [32:0] rs1, rs2, rs1_q, rs2_q;
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reg [32:0] rs1, rs2, rs1_q, rs2_q;
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reg [63:0] rd, rd_q;
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reg [63:0] rd, rd_q;
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wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
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reg pcpi_insn_valid_q;
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always @* begin
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always @* begin
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instr_mul = 0;
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instr_mul = 0;
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instr_mulh = 0;
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instr_mulh = 0;
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instr_mulhsu = 0;
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instr_mulhsu = 0;
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instr_mulhu = 0;
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instr_mulhu = 0;
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if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
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if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
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case (pcpi_insn[14:12])
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case (pcpi_insn[14:12])
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3'b000: instr_mul = 1;
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3'b000: instr_mul = 1;
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3'b001: instr_mulh = 1;
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3'b001: instr_mulh = 1;
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@ -1958,17 +1962,18 @@ module picorv32_pcpi_fast_mul #(
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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pcpi_insn_valid_q <= pcpi_insn_valid;
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rs1_q <= rs1;
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rs1_q <= rs1;
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rs2_q <= rs2;
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rs2_q <= rs2;
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rd_q <= rd;
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rd_q <= rd;
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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rd <= $signed(EXTRA_FFS ? rs1_q : rs1) * $signed(EXTRA_FFS ? rs2_q : rs2);
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rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (instr_any_mul && !(EXTRA_FFS ? active[3:0] : active[1:0])) begin
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if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
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if (instr_rs1_signed)
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if (instr_rs1_signed)
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rs1 <= $signed(pcpi_rs1);
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rs1 <= $signed(pcpi_rs1);
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else
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else
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@ -1990,10 +1995,10 @@ module picorv32_pcpi_fast_mul #(
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active <= 0;
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active <= 0;
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end
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end
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assign pcpi_wr = active[EXTRA_FFS ? 3 : 1];
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assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
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assign pcpi_wait = 0;
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assign pcpi_wait = 0;
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assign pcpi_ready = active[EXTRA_FFS ? 3 : 1];
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assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
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assign pcpi_rd = shift_out ? (EXTRA_FFS ? rd_q : rd) >> 32 : (EXTRA_FFS ? rd_q : rd);
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assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
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endmodule
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endmodule
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