mirror of https://github.com/YosysHQ/picorv32.git
Major redesign of main FSM
This commit is contained in:
parent
491cd5e15d
commit
e84f044bc5
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@ -1,14 +1,18 @@
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tests/*.o
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firmware/firmware.bin
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firmware/firmware.elf
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firmware/firmware.hex
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firmware/firmware.map
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testbench.exe
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testbench_axi.exe
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testbench.vcd
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dhrystone/dhry.bin
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dhrystone/dhry.elf
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dhrystone/dhry.hex
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dhrystone/dhry.map
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dhrystone/*.d
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dhrystone/*.o
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/tests/*.o
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/firmware/firmware.bin
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/firmware/firmware.elf
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/firmware/firmware.hex
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/firmware/firmware.map
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/dhrystone/dhry.bin
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/dhrystone/dhry.elf
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/dhrystone/dhry.hex
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/dhrystone/dhry.map
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/dhrystone/testbench.exe
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/dhrystone/testbench.vcd
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/dhrystone/timing.exe
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/dhrystone/timing.txt
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/dhrystone/*.d
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/dhrystone/*.o
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/testbench.exe
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/testbench_axi.exe
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/testbench.vcd
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32
README.md
32
README.md
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@ -46,26 +46,26 @@ interface, and communicating with the outside world via AXI4.
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Performance:
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------------
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The average Cycles per Instruction (CPI) is 5 to 7, depending on the
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mix of instructions in the code. The CPI for the individual instructions is:
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The average Cycles per Instruction (CPI) is 4 to 6, depending on the mix of
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instructions in the code. The CPI numbers for the individual instructions are:
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| Instruction | CPI |
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| ---------------------| ---:|
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| direct jump (jal) | 4 |
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| ALU reg + immediate | 4 |
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| ALU reg + reg | 5 |
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| branch (not taken) | 5 |
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| memory load | 7 |
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| memory store | 8 |
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| branch (taken) | 8 |
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| indirect jump (jalr) | 8 |
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| shift operations | 5+ |
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| Instruction | CPI |
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| ---------------------| ----:|
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| direct jump (jal) | 3 |
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| ALU reg + immediate | 3 |
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| ALU reg + reg | 4 |
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| branch (not taken) | 4 |
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| memory load | 5 |
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| memory store | 6 |
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| branch (taken) | 6 |
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| indirect jump (jalr) | 6 |
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| shift operations | 4-15 |
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Dhrystone benchmark results: 0.215 DMIPS/MHz (379 Dhrystones/Second/MHz)
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Dhrystone benchmark results: 0.280 DMIPS/MHz (493 Dhrystones/Second/MHz)
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For the Dryhstone benchmark the average CPI is 5.983.
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For the Dryhstone benchmark the average CPI is 4.606.
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*This numbers apply for setups with memory that can accomodate requests within
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*This numbers apply to systems with memory that can accomodate requests within
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one clock cycle. Slower memory will degrade the performance of the processor.*
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@ -5,10 +5,18 @@ CFLAGS = -MD -O3 -m32 -march=RV32I -ffreestanding -nostdlib -DTIME -DRISCV
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test: testbench.exe dhry.hex
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vvp -N testbench.exe
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timing: timing.exe dhry.hex
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vvp -N timing.exe > timing.txt
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sed 's,.*## ,,' timing.txt | gawk 'x != "" {print x,$$2-y;} {x=$$1;y=$$2;}' | sort | uniq -c | sort -k3 -n
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testbench.exe: testbench.v ../picorv32.v
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iverilog -o testbench.exe testbench.v ../picorv32.v
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chmod -x testbench.exe
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timing.exe: testbench.v ../picorv32.v
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iverilog -o timing.exe -DTIMING testbench.v ../picorv32.v
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chmod -x timing.exe
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dhry.hex: dhry.bin ../firmware/makehex.py
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python3 ../firmware/makehex.py $< > $@
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@ -27,7 +35,7 @@ dhry.elf: $(OBJS) ../firmware/sections.lds
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riscv64-unknown-elf-gcc -c $(CFLAGS) $<
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clean:
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd timing.exe timing.txt
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.PHONY: test clean
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@ -17,6 +17,16 @@ start:
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sw a2,0(a0)
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sw a5,0(a0)
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/* execute some insns for "make timing" */
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lui a0,0
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auipc a0,0
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slli a0,a0,0
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slli a0,a0,31
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addi a1,zero,0
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sll a0,a0,a1
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addi a1,zero,31
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sll a0,a0,a1
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/* set stack pointer */
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lui sp,(64*1024)>>12
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@ -43,11 +43,12 @@ module testbench;
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assign mem_ready = 1;
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always @(posedge clk) begin
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mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx;
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if (mem_la_read)
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mem_rdata <= memory[mem_la_addr >> 2];
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if (mem_valid) begin
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case (mem_addr)
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32'h1000_0000: begin
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`ifndef INSN_TIMING
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`ifndef TIMING
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$write("%c", mem_wdata);
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$fflush();
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`endif
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@ -75,14 +76,12 @@ module testbench;
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end
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end
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`ifdef INSN_TIMING
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`ifdef TIMING
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initial begin
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repeat (100000) @(posedge clk);
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$finish;
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end
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always @(uut.count_instr[0]) begin
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// iverilog -DINSN_TIMING testbench.v ../picorv32.v && ./a.out > x
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// sed 's,.*## ,,' x | gawk 'x != "" {print x,$2-y;} {x=$1;y=$2;}' | sort | uniq -c | sort -k3 -n
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$display("## %-s %d", uut.instruction, uut.count_cycle);
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end
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`endif
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@ -50,7 +50,6 @@ start:
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TEST(or)
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TEST(and)
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TEST(fence_i)
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TEST(simple)
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/* set stack pointer */
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417
picorv32.v
417
picorv32.v
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@ -49,12 +49,11 @@ module picorv32 #(
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localparam integer regindex_bits = ENABLE_REGS_16_31 ? 5 : 4;
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reg [63:0] count_cycle, count_instr;
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reg [31:0] reg_pc, reg_op1, reg_op2, reg_out;
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reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out, reg_alu_out;
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reg [31:0] cpuregs [0:regfile_size-1];
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reg [4:0] reg_sh;
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wire reg_out_0 = reg_out[0];
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wire [31:0] next_pc;
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// Memory Interface
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@ -65,24 +64,47 @@ module picorv32 #(
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reg mem_do_rinst;
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reg mem_do_rdata;
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reg mem_do_wdata;
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reg mem_done;
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wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
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wire mem_done = mem_ready && ((mem_state[0] && (mem_do_rinst || mem_do_rdata)) || mem_state == 2);
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assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);
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assign mem_la_addr = mem_do_prefetch ? reg_pc + 4 : mem_do_rinst ? reg_pc : {reg_op1[31:2], 2'b00};
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assign mem_la_addr = mem_do_prefetch || mem_do_rinst ? next_pc : {reg_op1[31:2], 2'b00};
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always @* begin
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(* full_case *)
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case (mem_wordsize)
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0: begin
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mem_buffer = mem_rdata;
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end
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1: begin
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case (reg_op1[1])
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1'b0: mem_buffer = mem_rdata[15: 0];
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1'b1: mem_buffer = mem_rdata[31:16];
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endcase
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end
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2: begin
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case (reg_op1[1:0])
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2'b00: mem_buffer = mem_rdata[ 7: 0];
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2'b01: mem_buffer = mem_rdata[15: 8];
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2'b10: mem_buffer = mem_rdata[23:16];
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2'b11: mem_buffer = mem_rdata[31:24];
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endcase
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end
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endcase
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end
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always @(posedge clk) begin
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mem_done <= 0;
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if (!resetn) begin
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mem_state <= 0;
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mem_valid <= 0;
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end else case (mem_state)
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0: begin
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mem_addr <= mem_la_addr;
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if (mem_do_rinst || mem_do_prefetch || mem_do_rdata) begin
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if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
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mem_valid <= 1;
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mem_instr <= mem_do_rinst || mem_do_rdata;
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mem_instr <= mem_do_prefetch || mem_do_rinst;
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mem_wstrb <= 0;
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mem_state <= 1;
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end
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end
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1: begin
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if (mem_ready) begin
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(* full_case *)
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case (mem_wordsize)
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0: begin
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mem_buffer <= mem_rdata;
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end
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1: begin
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case (reg_op1[1])
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1'b0: mem_buffer <= mem_rdata[15: 0];
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1'b1: mem_buffer <= mem_rdata[31:16];
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endcase
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end
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2: begin
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case (reg_op1[1:0])
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2'b00: mem_buffer <= mem_rdata[ 7: 0];
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2'b01: mem_buffer <= mem_rdata[15: 8];
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2'b10: mem_buffer <= mem_rdata[23:16];
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2'b11: mem_buffer <= mem_rdata[31:24];
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endcase
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end
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endcase
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mem_valid <= 0;
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mem_state <= 3;
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mem_done <= mem_do_rinst || mem_do_rdata;
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mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
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end
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end
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2: begin
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if (mem_ready) begin
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mem_valid <= 0;
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mem_state <= 3;
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mem_done <= 1;
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mem_state <= 0;
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end
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end
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3: begin
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if (mem_done)
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if (mem_do_rinst) begin
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mem_state <= 0;
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else if (mem_do_rinst || mem_do_rdata)
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mem_done <= 1;
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end
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end
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endcase
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end
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@ -159,7 +158,7 @@ module picorv32 #(
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reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
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reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
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reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
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reg instr_fence, instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh;
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reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh;
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wire instr_trap;
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reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
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@ -167,7 +166,7 @@ module picorv32 #(
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reg decoder_trigger;
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wire [31:0] decoded_imm_uj;
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assign { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } = $signed({mem_buffer[31:12], 1'b0});
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assign { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } = $signed({mem_rdata[31:12], 1'b0});
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reg is_lui_auipc_jal;
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reg is_lb_lh_lw_lbu_lhu;
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@ -200,7 +199,7 @@ module picorv32 #(
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instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
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instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
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instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
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instr_fence, instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
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instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
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reg [63:0] instruction;
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@ -248,7 +247,6 @@ module picorv32 #(
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if (instr_or) instruction = "or";
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if (instr_and) instruction = "and";
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if (instr_fence) instruction = "fence";
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if (instr_rdcycle) instruction = "rdcycle";
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if (instr_rdcycleh) instruction = "rdcycleh";
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if (instr_rdinstr) instruction = "rdinstr";
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@ -259,64 +257,61 @@ module picorv32 #(
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decoder_trigger <= 0;
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if (mem_do_rinst && mem_done) begin
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instr_lui <= mem_buffer[6:0] == 7'b0110111;
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instr_auipc <= mem_buffer[6:0] == 7'b0010111;
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instr_lui <= mem_rdata[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata[6:0] == 7'b0010111;
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instr_jal <= mem_buffer[6:0] == 7'b1101111;
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instr_jalr <= mem_buffer[6:0] == 7'b1100111;
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instr_jal <= mem_rdata[6:0] == 7'b1101111;
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instr_jalr <= mem_rdata[6:0] == 7'b1100111;
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instr_beq <= mem_buffer[6:0] == 7'b1100011 && mem_buffer[14:12] == 3'b000;
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instr_bne <= mem_buffer[6:0] == 7'b1100011 && mem_buffer[14:12] == 3'b001;
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instr_blt <= mem_buffer[6:0] == 7'b1100011 && mem_buffer[14:12] == 3'b100;
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instr_bge <= mem_buffer[6:0] == 7'b1100011 && mem_buffer[14:12] == 3'b101;
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instr_bltu <= mem_buffer[6:0] == 7'b1100011 && mem_buffer[14:12] == 3'b110;
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instr_bgeu <= mem_buffer[6:0] == 7'b1100011 && mem_buffer[14:12] == 3'b111;
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instr_beq <= mem_rdata[6:0] == 7'b1100011 && mem_rdata[14:12] == 3'b000;
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instr_bne <= mem_rdata[6:0] == 7'b1100011 && mem_rdata[14:12] == 3'b001;
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instr_blt <= mem_rdata[6:0] == 7'b1100011 && mem_rdata[14:12] == 3'b100;
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instr_bge <= mem_rdata[6:0] == 7'b1100011 && mem_rdata[14:12] == 3'b101;
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instr_bltu <= mem_rdata[6:0] == 7'b1100011 && mem_rdata[14:12] == 3'b110;
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instr_bgeu <= mem_rdata[6:0] == 7'b1100011 && mem_rdata[14:12] == 3'b111;
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instr_lb <= mem_buffer[6:0] == 7'b0000011 && mem_buffer[14:12] == 3'b000;
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instr_lh <= mem_buffer[6:0] == 7'b0000011 && mem_buffer[14:12] == 3'b001;
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instr_lw <= mem_buffer[6:0] == 7'b0000011 && mem_buffer[14:12] == 3'b010;
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instr_lbu <= mem_buffer[6:0] == 7'b0000011 && mem_buffer[14:12] == 3'b100;
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instr_lhu <= mem_buffer[6:0] == 7'b0000011 && mem_buffer[14:12] == 3'b101;
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instr_lb <= mem_rdata[6:0] == 7'b0000011 && mem_rdata[14:12] == 3'b000;
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instr_lh <= mem_rdata[6:0] == 7'b0000011 && mem_rdata[14:12] == 3'b001;
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instr_lw <= mem_rdata[6:0] == 7'b0000011 && mem_rdata[14:12] == 3'b010;
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instr_lbu <= mem_rdata[6:0] == 7'b0000011 && mem_rdata[14:12] == 3'b100;
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instr_lhu <= mem_rdata[6:0] == 7'b0000011 && mem_rdata[14:12] == 3'b101;
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instr_sb <= mem_buffer[6:0] == 7'b0100011 && mem_buffer[14:12] == 3'b000;
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instr_sh <= mem_buffer[6:0] == 7'b0100011 && mem_buffer[14:12] == 3'b001;
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instr_sw <= mem_buffer[6:0] == 7'b0100011 && mem_buffer[14:12] == 3'b010;
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instr_sb <= mem_rdata[6:0] == 7'b0100011 && mem_rdata[14:12] == 3'b000;
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instr_sh <= mem_rdata[6:0] == 7'b0100011 && mem_rdata[14:12] == 3'b001;
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instr_sw <= mem_rdata[6:0] == 7'b0100011 && mem_rdata[14:12] == 3'b010;
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instr_addi <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b000;
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instr_slti <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b010;
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instr_sltiu <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b011;
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instr_xori <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b100;
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instr_ori <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b110;
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instr_andi <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b111;
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instr_addi <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b000;
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instr_slti <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b010;
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instr_sltiu <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b011;
|
||||
instr_xori <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b100;
|
||||
instr_ori <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b110;
|
||||
instr_andi <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b111;
|
||||
|
||||
instr_slli <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b001 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_srli <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b101 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_srai <= mem_buffer[6:0] == 7'b0010011 && mem_buffer[14:12] == 3'b101 && mem_buffer[31:25] == 7'b0100000;
|
||||
instr_slli <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b001 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_srli <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b101 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_srai <= mem_rdata[6:0] == 7'b0010011 && mem_rdata[14:12] == 3'b101 && mem_rdata[31:25] == 7'b0100000;
|
||||
|
||||
instr_add <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b000 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_sub <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b000 && mem_buffer[31:25] == 7'b0100000;
|
||||
instr_sll <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b001 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_slt <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b010 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_sltu <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b011 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_xor <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b100 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_srl <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b101 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_sra <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b101 && mem_buffer[31:25] == 7'b0100000;
|
||||
instr_or <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b110 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_and <= mem_buffer[6:0] == 7'b0110011 && mem_buffer[14:12] == 3'b111 && mem_buffer[31:25] == 7'b0000000;
|
||||
instr_add <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b000 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_sub <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b000 && mem_rdata[31:25] == 7'b0100000;
|
||||
instr_sll <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b001 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_slt <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b010 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_sltu <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b011 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_xor <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b100 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_srl <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b101 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_sra <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b101 && mem_rdata[31:25] == 7'b0100000;
|
||||
instr_or <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b110 && mem_rdata[31:25] == 7'b0000000;
|
||||
instr_and <= mem_rdata[6:0] == 7'b0110011 && mem_rdata[14:12] == 3'b111 && mem_rdata[31:25] == 7'b0000000;
|
||||
|
||||
instr_fence <= (mem_buffer[6:0] == 7'b0001111 && mem_buffer[19:12] == 0 && mem_buffer[31:28] == 4'b0000) ||
|
||||
(mem_buffer[6:0] == 7'b0001111 && mem_buffer[31:12] == 1);
|
||||
instr_rdcycle <= ((mem_rdata[6:0] == 7'b1110011 && mem_rdata[31:12] == 'b11000000000000000010) ||
|
||||
(mem_rdata[6:0] == 7'b1110011 && mem_rdata[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
|
||||
instr_rdcycleh <= ((mem_rdata[6:0] == 7'b1110011 && mem_rdata[31:12] == 'b11001000000000000010) ||
|
||||
(mem_rdata[6:0] == 7'b1110011 && mem_rdata[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS;
|
||||
instr_rdinstr <= (mem_rdata[6:0] == 7'b1110011 && mem_rdata[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
|
||||
instr_rdinstrh <= (mem_rdata[6:0] == 7'b1110011 && mem_rdata[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS;
|
||||
|
||||
instr_rdcycle <= ((mem_buffer[6:0] == 7'b1110011 && mem_buffer[31:12] == 'b11000000000000000010) ||
|
||||
(mem_buffer[6:0] == 7'b1110011 && mem_buffer[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
|
||||
instr_rdcycleh <= ((mem_buffer[6:0] == 7'b1110011 && mem_buffer[31:12] == 'b11001000000000000010) ||
|
||||
(mem_buffer[6:0] == 7'b1110011 && mem_buffer[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS;
|
||||
instr_rdinstr <= (mem_buffer[6:0] == 7'b1110011 && mem_buffer[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
|
||||
instr_rdinstrh <= (mem_buffer[6:0] == 7'b1110011 && mem_buffer[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS;
|
||||
|
||||
decoded_rd <= mem_buffer[11:7];
|
||||
decoded_rs1 <= mem_buffer[19:15];
|
||||
decoded_rs2 <= mem_buffer[24:20];
|
||||
decoded_rd <= mem_rdata[11:7];
|
||||
decoded_rs1 <= mem_rdata[19:15];
|
||||
decoded_rs2 <= mem_rdata[24:20];
|
||||
|
||||
decoder_trigger <= 1;
|
||||
end
|
||||
|
@ -325,19 +320,19 @@ module picorv32 #(
|
|||
(* parallel_case *)
|
||||
case (1'b1)
|
||||
|{instr_lui, instr_auipc}:
|
||||
decoded_imm <= mem_buffer[31:12] << 12;
|
||||
decoded_imm <= mem_rdata[31:12] << 12;
|
||||
instr_jal:
|
||||
decoded_imm <= decoded_imm_uj;
|
||||
instr_jalr:
|
||||
decoded_imm <= $signed(mem_buffer[31:20]);
|
||||
decoded_imm <= $signed(mem_rdata[31:20]);
|
||||
|{instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu}:
|
||||
decoded_imm <= $signed({mem_buffer[31], mem_buffer[7], mem_buffer[30:25], mem_buffer[11:8], 1'b0});
|
||||
decoded_imm <= $signed({mem_rdata[31], mem_rdata[7], mem_rdata[30:25], mem_rdata[11:8], 1'b0});
|
||||
|{instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu}:
|
||||
decoded_imm <= $signed(mem_buffer[31:20]);
|
||||
decoded_imm <= $signed(mem_rdata[31:20]);
|
||||
|{instr_sb, instr_sh, instr_sw}:
|
||||
decoded_imm <= $signed({mem_buffer[31:25], mem_buffer[11:7]});
|
||||
decoded_imm <= $signed({mem_rdata[31:25], mem_rdata[11:7]});
|
||||
|{instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi}:
|
||||
decoded_imm <= $signed(mem_buffer[31:20]);
|
||||
decoded_imm <= $signed(mem_rdata[31:20]);
|
||||
default:
|
||||
decoded_imm <= 1'bx;
|
||||
endcase
|
||||
|
@ -347,46 +342,97 @@ module picorv32 #(
|
|||
|
||||
// Main State Machine
|
||||
|
||||
localparam cpu_state_fetch = 0;
|
||||
localparam cpu_state_ld_rs1 = 1;
|
||||
localparam cpu_state_ld_rs2 = 2;
|
||||
localparam cpu_state_exec = 3;
|
||||
localparam cpu_state_shift = 4;
|
||||
localparam cpu_state_store = 5;
|
||||
localparam cpu_state_trap = 0;
|
||||
localparam cpu_state_fetch = 1;
|
||||
localparam cpu_state_ld_rs1 = 2;
|
||||
localparam cpu_state_ld_rs2 = 3;
|
||||
localparam cpu_state_exec = 4;
|
||||
localparam cpu_state_shift = 5;
|
||||
localparam cpu_state_stmem = 6;
|
||||
localparam cpu_state_ldmem = 7;
|
||||
reg [2:0] cpu_state;
|
||||
|
||||
reg force_mem_do_rinst;
|
||||
reg force_mem_do_rdata;
|
||||
reg force_mem_do_wdata;
|
||||
reg set_mem_do_rinst;
|
||||
reg set_mem_do_rdata;
|
||||
reg set_mem_do_wdata;
|
||||
reg mask_decoder_trigger;
|
||||
reg force_decoder_trigger;
|
||||
|
||||
reg latched_store;
|
||||
reg latched_stalu;
|
||||
reg latched_branch;
|
||||
reg latched_is_lu;
|
||||
reg latched_is_lh;
|
||||
reg latched_is_lb;
|
||||
reg [regindex_bits-1:0] latched_rd;
|
||||
|
||||
reg [31:0] current_pc;
|
||||
assign next_pc = latched_store && latched_branch ? reg_out : reg_next_pc;
|
||||
|
||||
reg [31:0] alu_out;
|
||||
reg alu_out_0;
|
||||
|
||||
always @* begin
|
||||
alu_out_0 = 'bx;
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
instr_beq:
|
||||
alu_out_0 = reg_op1 == reg_op2;
|
||||
instr_bne:
|
||||
alu_out_0 = reg_op1 != reg_op2;
|
||||
instr_bge:
|
||||
alu_out_0 = $signed(reg_op1) >= $signed(reg_op2);
|
||||
instr_bgeu:
|
||||
alu_out_0 = reg_op1 >= reg_op2;
|
||||
is_slti_blt_slt:
|
||||
alu_out_0 = $signed(reg_op1) < $signed(reg_op2);
|
||||
is_sltiu_bltu_sltu:
|
||||
alu_out_0 = reg_op1 < reg_op2;
|
||||
endcase
|
||||
|
||||
alu_out = 'bx;
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
is_lui_auipc_jal_jalr_addi_add:
|
||||
alu_out = reg_op1 + reg_op2;
|
||||
instr_sub:
|
||||
alu_out = reg_op1 - reg_op2;
|
||||
|{instr_beq, instr_bne, instr_bge, instr_bgeu, is_slti_blt_slt, is_sltiu_bltu_sltu}:
|
||||
alu_out = alu_out_0;
|
||||
instr_xori || instr_xor:
|
||||
alu_out = reg_op1 ^ reg_op2;
|
||||
instr_ori || instr_or:
|
||||
alu_out = reg_op1 | reg_op2;
|
||||
instr_andi || instr_and:
|
||||
alu_out = reg_op1 & reg_op2;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
trap <= 0;
|
||||
reg_sh <= 'bx;
|
||||
reg_out <= 'bx;
|
||||
force_mem_do_rinst = 0;
|
||||
force_mem_do_rdata = 0;
|
||||
force_mem_do_wdata = 0;
|
||||
set_mem_do_rinst = 0;
|
||||
set_mem_do_rdata = 0;
|
||||
set_mem_do_wdata = 0;
|
||||
mask_decoder_trigger <= 0;
|
||||
force_decoder_trigger <= 0;
|
||||
|
||||
reg_alu_out <= alu_out;
|
||||
|
||||
if (ENABLE_COUNTERS)
|
||||
count_cycle <= resetn ? count_cycle + 1 : 0;
|
||||
|
||||
if (!resetn) begin
|
||||
trap <= 0;
|
||||
reg_pc <= 0;
|
||||
reg_next_pc <= 0;
|
||||
reg_op1 <= 'bx;
|
||||
reg_op2 <= 'bx;
|
||||
if (ENABLE_COUNTERS)
|
||||
count_instr <= 0;
|
||||
latched_store <= 0;
|
||||
latched_stalu <= 0;
|
||||
latched_branch <= 0;
|
||||
latched_is_lu <= 0;
|
||||
latched_is_lh <= 0;
|
||||
latched_is_lb <= 0;
|
||||
|
@ -394,41 +440,58 @@ module picorv32 #(
|
|||
end else
|
||||
(* parallel_case, full_case *)
|
||||
case (cpu_state)
|
||||
cpu_state_trap: begin
|
||||
trap <= 1;
|
||||
end
|
||||
cpu_state_fetch: begin
|
||||
mem_do_rinst <= (!decoder_trigger || mask_decoder_trigger) && !trap && !force_decoder_trigger;
|
||||
mem_do_prefetch <= 0;
|
||||
mem_do_rinst <= (!decoder_trigger || mask_decoder_trigger) && !force_decoder_trigger;
|
||||
mem_wordsize <= 0;
|
||||
|
||||
if (latched_is_lu || latched_is_lh || latched_is_lb) begin
|
||||
current_pc = reg_next_pc;
|
||||
|
||||
if (latched_branch) begin
|
||||
current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc;
|
||||
`ifdef DEBUG
|
||||
$display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);
|
||||
`endif
|
||||
cpuregs[latched_rd] <= reg_pc + 4;
|
||||
end else
|
||||
if (latched_store) begin
|
||||
`ifdef DEBUG
|
||||
$display("ST_RD: %2d 0x%08x", latched_rd, reg_out);
|
||||
`endif
|
||||
cpuregs[latched_rd] <= reg_out;
|
||||
cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out;
|
||||
end
|
||||
|
||||
reg_pc <= current_pc;
|
||||
reg_next_pc <= current_pc;
|
||||
|
||||
latched_store <= 0;
|
||||
latched_stalu <= 0;
|
||||
latched_branch <= 0;
|
||||
latched_is_lu <= 0;
|
||||
latched_is_lh <= 0;
|
||||
latched_is_lb <= 0;
|
||||
latched_rd <= decoded_rd;
|
||||
|
||||
if ((decoder_trigger && !mask_decoder_trigger) || force_decoder_trigger) begin
|
||||
`ifdef DEBUG
|
||||
$display("DECODE: 0x%08x %-s", reg_pc, instruction);
|
||||
$display("DECODE: 0x%08x %-s", current_pc, instruction);
|
||||
`endif
|
||||
reg_next_pc <= current_pc + 4;
|
||||
|
||||
if (instr_trap) begin
|
||||
trap <= 1;
|
||||
end else if (instr_fence) begin
|
||||
mem_do_rinst <= 1;
|
||||
reg_pc <= reg_pc + 4;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
`ifdef DEBUG
|
||||
$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", current_pc);
|
||||
`endif
|
||||
cpu_state <= cpu_state_trap;
|
||||
end else if (instr_jal) begin
|
||||
mem_do_rinst <= 1;
|
||||
reg_out <= reg_pc + 4;
|
||||
if (latched_is_lu || latched_is_lh || latched_is_lb)
|
||||
reg_pc <= reg_pc + decoded_imm;
|
||||
reg_next_pc <= current_pc + decoded_imm;
|
||||
else
|
||||
reg_pc <= reg_pc + decoded_imm_uj;
|
||||
latched_rd <= decoded_rd;
|
||||
cpu_state <= cpu_state_store;
|
||||
reg_next_pc <= current_pc + decoded_imm_uj;
|
||||
latched_branch <= 1;
|
||||
end else if (|{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}) begin
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
|
@ -441,9 +504,9 @@ module picorv32 #(
|
|||
instr_rdinstrh:
|
||||
reg_out <= count_instr[63:32];
|
||||
endcase
|
||||
latched_rd <= decoded_rd;
|
||||
cpu_state <= cpu_state_store;
|
||||
latched_store <= 1;
|
||||
end else begin
|
||||
mem_do_rinst <= 0;
|
||||
mem_do_prefetch <= !instr_jalr;
|
||||
cpu_state <= cpu_state_ld_rs1;
|
||||
end
|
||||
|
@ -493,40 +556,30 @@ module picorv32 #(
|
|||
end
|
||||
end
|
||||
cpu_state_exec: begin
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
is_lui_auipc_jal_jalr_addi_add:
|
||||
reg_out <= reg_op1 + reg_op2;
|
||||
instr_sub:
|
||||
reg_out <= reg_op1 - reg_op2;
|
||||
instr_beq:
|
||||
reg_out <= {31'bx, reg_op1 == reg_op2};
|
||||
instr_bne:
|
||||
reg_out <= {31'bx, reg_op1 != reg_op2};
|
||||
instr_bge:
|
||||
reg_out <= {31'bx, $signed(reg_op1) >= $signed(reg_op2)};
|
||||
instr_bgeu:
|
||||
reg_out <= {31'bx, reg_op1 >= reg_op2};
|
||||
is_slti_blt_slt:
|
||||
reg_out <= $signed(reg_op1) < $signed(reg_op2);
|
||||
is_sltiu_bltu_sltu:
|
||||
reg_out <= reg_op1 < reg_op2;
|
||||
instr_xori || instr_xor:
|
||||
reg_out <= reg_op1 ^ reg_op2;
|
||||
instr_ori || instr_or:
|
||||
reg_out <= reg_op1 | reg_op2;
|
||||
instr_andi || instr_and:
|
||||
reg_out <= reg_op1 & reg_op2;
|
||||
endcase
|
||||
latched_rd <= decoded_rd;
|
||||
cpu_state <= cpu_state_store;
|
||||
reg_out <= reg_pc + decoded_imm;
|
||||
if (is_beq_bne_blt_bge_bltu_bgeu) begin
|
||||
latched_rd <= 0;
|
||||
if (mem_done)
|
||||
cpu_state <= cpu_state_fetch;
|
||||
if (alu_out_0) begin
|
||||
latched_store <= 1;
|
||||
latched_branch <= 1;
|
||||
mask_decoder_trigger <= 1;
|
||||
set_mem_do_rinst = 1;
|
||||
end
|
||||
end else begin
|
||||
latched_branch <= instr_jalr;
|
||||
latched_store <= 1;
|
||||
latched_stalu <= 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end
|
||||
end
|
||||
cpu_state_shift: begin
|
||||
if (reg_sh == 0) begin
|
||||
reg_out <= reg_op1;
|
||||
mem_do_rinst <= mem_do_prefetch;
|
||||
latched_rd <= decoded_rd;
|
||||
cpu_state <= cpu_state_store;
|
||||
latched_store <= 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end else if (reg_sh >= 4) begin
|
||||
(* parallel_case, full_case *)
|
||||
case (1'b1)
|
||||
|
@ -545,41 +598,6 @@ module picorv32 #(
|
|||
reg_sh <= reg_sh - 1;
|
||||
end
|
||||
end
|
||||
cpu_state_store: begin
|
||||
mem_do_rinst <= mem_do_prefetch || mem_do_rinst;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
if (instr_jal) begin
|
||||
`ifdef DEBUG
|
||||
$display("ST_RD: %2d 0x%08x", latched_rd, reg_out);
|
||||
`endif
|
||||
cpuregs[latched_rd] <= reg_out;
|
||||
end else if (instr_jalr) begin
|
||||
`ifdef DEBUG
|
||||
$display("ST_RD: %2d 0x%08x", latched_rd, reg_pc + 4);
|
||||
`endif
|
||||
cpuregs[latched_rd] <= reg_pc + 4;
|
||||
reg_pc <= reg_out;
|
||||
end else if (is_beq_bne_blt_bge_bltu_bgeu) begin
|
||||
if (reg_out_0) begin
|
||||
if (mem_done) begin
|
||||
force_mem_do_rinst = 1;
|
||||
mask_decoder_trigger <= 1;
|
||||
reg_pc <= reg_pc + decoded_imm;
|
||||
end else begin
|
||||
/* waiting for mem_done */
|
||||
cpu_state <= cpu_state_store;
|
||||
reg_out[0] <= reg_out_0;
|
||||
end
|
||||
end else
|
||||
reg_pc <= reg_pc + 4;
|
||||
end else begin
|
||||
`ifdef DEBUG
|
||||
$display("ST_RD: %2d 0x%08x", latched_rd, reg_out);
|
||||
`endif
|
||||
cpuregs[latched_rd] <= reg_out;
|
||||
reg_pc <= reg_pc + 4;
|
||||
end
|
||||
end
|
||||
cpu_state_stmem: begin
|
||||
if (!mem_do_prefetch || mem_done) begin
|
||||
if (!mem_do_wdata) begin
|
||||
|
@ -590,10 +608,9 @@ module picorv32 #(
|
|||
instr_sw: mem_wordsize <= 0;
|
||||
endcase
|
||||
reg_op1 <= reg_op1 + decoded_imm;
|
||||
force_mem_do_wdata = 1;
|
||||
set_mem_do_wdata = 1;
|
||||
end
|
||||
if (!mem_do_prefetch && mem_done) begin
|
||||
reg_pc <= reg_pc + 4;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
force_decoder_trigger <= 1;
|
||||
end
|
||||
|
@ -608,12 +625,12 @@ module picorv32 #(
|
|||
instr_lh || instr_lhu: mem_wordsize <= 1;
|
||||
instr_lw: mem_wordsize <= 0;
|
||||
endcase
|
||||
latched_store <= 1;
|
||||
latched_is_lu <= is_lbu_lhu_lw;
|
||||
latched_is_lh <= instr_lh;
|
||||
latched_is_lb <= instr_lb;
|
||||
latched_rd <= decoded_rd;
|
||||
reg_op1 <= reg_op1 + decoded_imm;
|
||||
force_mem_do_rdata = 1;
|
||||
set_mem_do_rdata = 1;
|
||||
end
|
||||
if (!mem_do_prefetch && mem_done) begin
|
||||
(* parallel_case, full_case *)
|
||||
|
@ -622,7 +639,6 @@ module picorv32 #(
|
|||
latched_is_lh: reg_out <= $signed(mem_buffer[15:0]);
|
||||
latched_is_lb: reg_out <= $signed(mem_buffer[7:0]);
|
||||
endcase
|
||||
reg_pc <= reg_pc + 4;
|
||||
force_decoder_trigger <= 1;
|
||||
cpu_state <= cpu_state_fetch;
|
||||
end
|
||||
|
@ -635,20 +651,20 @@ module picorv32 #(
|
|||
`ifdef DEBUG
|
||||
$display("MISALIGNED WORD: 0x%08x", reg_op1);
|
||||
`endif
|
||||
trap <= 1;
|
||||
cpu_state <= cpu_state_trap;
|
||||
end
|
||||
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
|
||||
`ifdef DEBUG
|
||||
$display("MISALIGNED HALFWORD: 0x%08x", reg_op1);
|
||||
`endif
|
||||
trap <= 1;
|
||||
cpu_state <= cpu_state_trap;
|
||||
end
|
||||
end
|
||||
if (resetn && mem_do_rinst && reg_pc[1:0] != 0) begin
|
||||
`ifdef DEBUG
|
||||
$display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);
|
||||
`endif
|
||||
trap <= 1;
|
||||
cpu_state <= cpu_state_trap;
|
||||
end
|
||||
|
||||
if (!resetn || mem_done) begin
|
||||
|
@ -658,15 +674,16 @@ module picorv32 #(
|
|||
mem_do_wdata <= 0;
|
||||
end
|
||||
|
||||
if (force_mem_do_rinst)
|
||||
if (set_mem_do_rinst)
|
||||
mem_do_rinst <= 1;
|
||||
if (force_mem_do_rdata)
|
||||
if (set_mem_do_rdata)
|
||||
mem_do_rdata <= 1;
|
||||
if (force_mem_do_wdata)
|
||||
if (set_mem_do_wdata)
|
||||
mem_do_wdata <= 1;
|
||||
|
||||
// optimize for 32bit instr alignment
|
||||
reg_pc[1:0] <= 0;
|
||||
reg_next_pc[1:0] <= 0;
|
||||
current_pc = 'bx;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
|
@ -1,53 +0,0 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# fence_i.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test self-modifying code and the fence.i instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
li a3, 111
|
||||
la a0, 3f
|
||||
la a1, 1f
|
||||
la a2, 2f
|
||||
lw a0, 0(a0)
|
||||
|
||||
# test I$ hit
|
||||
.align 6
|
||||
sw a0, 0(a1)
|
||||
fence.i
|
||||
|
||||
1: addi a3, a3, 222
|
||||
TEST_CASE( 2, a3, 444, nop )
|
||||
|
||||
# test prefetcher hit
|
||||
li a4, 100
|
||||
1: addi a4, a4, -1
|
||||
bnez a4, 1b
|
||||
|
||||
sw a0, 0(a2)
|
||||
fence.i
|
||||
|
||||
.align 6
|
||||
2: addi a3, a3, 555
|
||||
TEST_CASE( 3, a3, 777, nop )
|
||||
|
||||
3: addi a3, a3, 333
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
Loading…
Reference in New Issue