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testbench_wb: Add proper attribution for wb_ram module

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Olof Kindgren 2017-12-27 20:38:19 +01:00
parent 0495ce8b5a
commit f1949e9bf1
1 changed files with 19 additions and 0 deletions
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testbench_wb.v
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@ -166,6 +166,25 @@ module picorv32_wrapper #(
end
endmodule
/* ISC License
*
* Verilog on-chip RAM with Wishbone interface
*
* Copyright (C) 2014, 2016 Olof Kindgren <olof.kindgren@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_ram #(
parameter depth = 256,
parameter memfile = "",