mirror of https://github.com/YosysHQ/picorv32.git
Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench
This commit is contained in:
Clifford Wolf
parent
bb9ebeb9e3
commit
f295b900bc
6
Makefile
6
Makefile
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@ -47,15 +47,15 @@ test_synth: testbench_synth.vvp firmware/firmware.hex
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vvp -N $<
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testbench.vvp: testbench.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL $^
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_wb.vvp: testbench_wb.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL $^
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
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chmod -x $@
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testbench_sp.vvp: testbench.v picorv32.v
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL -DSP_TEST $^
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iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^
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chmod -x $@
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testbench_synth.vvp: testbench.v synth.v
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80
picorv32.v
80
picorv32.v
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@ -2386,6 +2386,26 @@ module picorv32_axi #(
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input [31:0] irq,
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output [31:0] eoi,
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`ifdef RISCV_FORMAL
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output rvfi_valid,
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output [ 7:0] rvfi_order,
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output [31:0] rvfi_insn,
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output rvfi_trap,
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output [ 4:0] rvfi_rs1_addr,
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output [ 4:0] rvfi_rs2_addr,
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output [31:0] rvfi_rs1_rdata,
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output [31:0] rvfi_rs2_rdata,
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output [ 4:0] rvfi_rd_addr,
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output [31:0] rvfi_rd_wdata,
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output [31:0] rvfi_pc_rdata,
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output [31:0] rvfi_pc_wdata,
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output [31:0] rvfi_mem_addr,
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output [ 3:0] rvfi_mem_rmask,
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output [ 3:0] rvfi_mem_wmask,
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output [31:0] rvfi_mem_rdata,
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output [31:0] rvfi_mem_wdata,
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`endif
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// Trace Interface
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output trace_valid,
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output [35:0] trace_data
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@ -2478,6 +2498,26 @@ module picorv32_axi #(
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.irq(irq),
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.eoi(eoi),
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`ifdef RISCV_FORMAL
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata(rvfi_rs1_rdata),
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.rvfi_rs2_rdata(rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask(rvfi_mem_rmask),
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.rvfi_mem_wmask(rvfi_mem_wmask),
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.rvfi_mem_rdata(rvfi_mem_rdata),
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.rvfi_mem_wdata(rvfi_mem_wdata),
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`endif
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.trace_valid(trace_valid),
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.trace_data (trace_data)
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);
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@ -2628,6 +2668,26 @@ module picorv32_wb #(
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input [31:0] irq,
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output [31:0] eoi,
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`ifdef RISCV_FORMAL
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output rvfi_valid,
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output [ 7:0] rvfi_order,
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output [31:0] rvfi_insn,
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output rvfi_trap,
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output [ 4:0] rvfi_rs1_addr,
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output [ 4:0] rvfi_rs2_addr,
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output [31:0] rvfi_rs1_rdata,
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output [31:0] rvfi_rs2_rdata,
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output [ 4:0] rvfi_rd_addr,
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output [31:0] rvfi_rd_wdata,
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output [31:0] rvfi_pc_rdata,
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output [31:0] rvfi_pc_wdata,
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output [31:0] rvfi_mem_addr,
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output [ 3:0] rvfi_mem_rmask,
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output [ 3:0] rvfi_mem_wmask,
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output [31:0] rvfi_mem_rdata,
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output [31:0] rvfi_mem_wdata,
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`endif
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// Trace Interface
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output trace_valid,
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output [35:0] trace_data,
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@ -2698,6 +2758,26 @@ module picorv32_wb #(
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.irq(irq),
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.eoi(eoi),
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`ifdef RISCV_FORMAL
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata(rvfi_rs1_rdata),
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.rvfi_rs2_rdata(rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask(rvfi_mem_rmask),
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.rvfi_mem_wmask(rvfi_mem_wmask),
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.rvfi_mem_rdata(rvfi_mem_rdata),
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.rvfi_mem_wdata(rvfi_mem_wdata),
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`endif
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.trace_valid(trace_valid),
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.trace_data (trace_data)
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);
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63
testbench.v
63
testbench.v
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@ -135,6 +135,26 @@ module picorv32_wrapper #(
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.tests_passed (tests_passed )
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);
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`ifdef RISCV_FORMAL
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wire rvfi_valid;
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wire [7:0] rvfi_order;
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wire [31:0] rvfi_insn;
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wire rvfi_trap;
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wire [4:0] rvfi_rs1_addr;
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wire [4:0] rvfi_rs2_addr;
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wire [31:0] rvfi_rs1_rdata;
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wire [31:0] rvfi_rs2_rdata;
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wire [4:0] rvfi_rd_addr;
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wire [31:0] rvfi_rd_wdata;
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wire [31:0] rvfi_pc_rdata;
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wire [31:0] rvfi_pc_wdata;
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wire [31:0] rvfi_mem_addr;
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wire [3:0] rvfi_mem_rmask;
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wire [3:0] rvfi_mem_wmask;
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wire [31:0] rvfi_mem_rdata;
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wire [31:0] rvfi_mem_wdata;
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`endif
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picorv32_axi #(
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`ifndef SYNTH_TEST
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`ifdef SP_TEST
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@ -170,10 +190,53 @@ module picorv32_wrapper #(
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.irq (irq ),
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`ifdef RISCV_FORMAL
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata ),
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.rvfi_rs2_rdata (rvfi_rs2_rdata ),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask (rvfi_mem_rmask ),
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.rvfi_mem_wmask (rvfi_mem_wmask ),
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.rvfi_mem_rdata (rvfi_mem_rdata ),
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.rvfi_mem_wdata (rvfi_mem_wdata ),
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`endif
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.trace_valid (trace_valid ),
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.trace_data (trace_data )
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);
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`ifdef RISCV_FORMAL
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riscv_formal_monitor_rv32ic rvfi_monitor (
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.clock (clk ),
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.reset (!resetn ),
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata(rvfi_rs1_rdata),
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.rvfi_rs2_rdata(rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask(rvfi_mem_rmask),
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.rvfi_mem_wmask(rvfi_mem_wmask),
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.rvfi_mem_rdata(rvfi_mem_rdata),
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.rvfi_mem_wdata(rvfi_mem_wdata)
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);
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`endif
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reg [1023:0] firmware_file;
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initial begin
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if (!$value$plusargs("firmware=%s", firmware_file))
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