mirror of https://github.com/YosysHQ/picorv32.git
Added rvfi_mem interface
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commit
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picorv32.v
30
picorv32.v
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@ -104,9 +104,10 @@ module picorv32 #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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output reg rvfi_valid,
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output reg rvfi_valid,
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output reg [4:0] rvfi_rs1,
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output reg [ 7:0] rvfi_order,
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output reg [4:0] rvfi_rs2,
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output reg [ 4:0] rvfi_rs1,
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output reg [4:0] rvfi_rd,
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output reg [ 4:0] rvfi_rs2,
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output reg [ 4:0] rvfi_rd,
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output reg [31:0] rvfi_insn,
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output reg [31:0] rvfi_insn,
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output reg [31:0] rvfi_pre_pc,
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output reg [31:0] rvfi_pre_pc,
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output reg [31:0] rvfi_pre_rs1,
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output reg [31:0] rvfi_pre_rs1,
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@ -114,6 +115,11 @@ module picorv32 #(
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output reg [31:0] rvfi_post_pc,
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output reg [31:0] rvfi_post_pc,
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output reg [31:0] rvfi_post_rd,
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output reg [31:0] rvfi_post_rd,
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output reg rvfi_post_trap,
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output reg rvfi_post_trap,
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output reg [31:0] rvfi_mem_addr,
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output reg [ 3:0] rvfi_mem_rmask,
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output reg [ 3:0] rvfi_mem_wmask,
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output reg [31:0] rvfi_mem_rdata,
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output reg [31:0] rvfi_mem_wdata,
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`endif
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`endif
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// Trace Interface
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// Trace Interface
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@ -1865,6 +1871,8 @@ module picorv32 #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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always @(posedge clk) begin
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always @(posedge clk) begin
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rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
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rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
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rvfi_order <= 0;
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rvfi_insn <= dbg_insn_opcode;
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rvfi_insn <= dbg_insn_opcode;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs2 <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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rvfi_rs2 <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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@ -1885,6 +1893,22 @@ module picorv32 #(
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rvfi_rd <= 0;
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rvfi_rd <= 0;
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rvfi_post_rd <= 0;
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rvfi_post_rd <= 0;
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end
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end
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if (dbg_mem_valid && dbg_mem_ready) begin
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if (dbg_mem_instr) begin
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rvfi_mem_addr <= 0;
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rvfi_mem_rmask <= 0;
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rvfi_mem_wmask <= 0;
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rvfi_mem_rdata <= 0;
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rvfi_mem_wdata <= 0;
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end else begin
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rvfi_mem_addr <= dbg_mem_addr;
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rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
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rvfi_mem_wmask <= dbg_mem_wstrb;
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rvfi_mem_rdata <= dbg_mem_rdata;
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rvfi_mem_wdata <= dbg_mem_wdata;
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end
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end
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end
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end
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always @* begin
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always @* begin
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