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Towards compressed ISA support

This commit is contained in:
Clifford Wolf 2015-11-19 14:01:33 +01:00
parent d8ffbf044a
commit f8eed23a68
1 changed files with 98 additions and 75 deletions
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27
picorv32.v
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@ -232,8 +232,9 @@ module picorv32 #(
always @(posedge clk) begin
if (mem_valid && mem_ready) begin
mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
end
if (COMPRESSED_ISA && mem_do_rinst) begin
if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
@ -271,6 +272,13 @@ module picorv32 #(
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
@ -288,6 +296,10 @@ module picorv32 #(
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
@ -319,7 +331,6 @@ module picorv32 #(
endcase
end
end
end
always @(posedge clk) begin
if (!resetn) begin
@ -584,6 +595,12 @@ module picorv32 #(
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // C.J
instr_jal <= 1;
@ -602,6 +619,12 @@ module picorv32 #(
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
3'b010: begin // C.LWSP
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];