Hardware
/
picorv32
mirror of https://github.com/YosysHQ/picorv32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Minor fixes in scripts/icestorm/

This commit is contained in:
Clifford Wolf 2016-07-14 09:07:52 +02:00
parent 288a043aca
commit f9da3f2ce8
2 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
scripts/icestorm/Makefile
View File

@ -18,11 +18,11 @@ firmware.hex: firmware.bin
synth.blif: example.v ../../picorv32.v firmware.hex synth.blif: example.v ../../picorv32.v firmware.hex
yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^) yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
example.txt: synth.blif example.asc: synth.blif
arachne-pnr -d 8k -o example.txt -p example.pcf synth.blif arachne-pnr -d 8k -o example.asc -p example.pcf synth.blif
example.bin: example.txt example.bin: example.asc
icepack example.txt example.bin icepack example.asc example.bin
example_tb.vvp: example_tb.v example.v firmware.hex example_tb.vvp: example_tb.v example.v firmware.hex
iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
@ -44,8 +44,8 @@ synth_sim: synth_tb.vvp
synth_sim_vcd: synth_tb.vvp synth_sim_vcd: synth_tb.vvp
vvp -N synth_tb.vvp +vcd vvp -N synth_tb.vvp +vcd
route.v: example.txt route.v: example.asc
icebox_vlog -L -n top -sp example.pcf example.txt > route.v icebox_vlog -L -n top -sp example.pcf example.asc > route.v
route_tb.vvp: example_tb.v route.v route_tb.vvp: example_tb.v route.v
iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
@ -65,7 +65,7 @@ view:
clean: clean:
rm -f firmware.elf firmware.map firmware.bin firmware.hex rm -f firmware.elf firmware.map firmware.bin firmware.hex
rm -f synth.log synth.v synth.blif route.v example.txt example.bin rm -f synth.log synth.v synth.blif route.v example.asc example.bin
rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
.PHONY: all prog_sram view clean .PHONY: all prog_sram view clean

8
scripts/icestorm/example_tb.v
View File

@ -1,12 +1,12 @@
`timescale 1 ns / 1 ps `timescale 1 ns / 1 ps
module testbench; module testbench;
reg clk_pin = 1; reg clk = 1;
always #5 clk_pin = ~clk_pin; always #5 clk = ~clk;
wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7; wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;
top uut ( top uut (
.clk_pin(clk_pin), .clk(clk),
.LED0(LED0), .LED0(LED0),
.LED1(LED1), .LED1(LED1),
.LED2(LED2), .LED2(LED2),
@ -24,7 +24,7 @@ module testbench;
end end
$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0); $monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
repeat (10000) @(posedge clk_pin); repeat (10000) @(posedge clk);
$finish; $finish;
end end
endmodule endmodule