mirror of https://github.com/YosysHQ/picorv32.git
Fixed dbg_ signals: no latches (formal verification doesn't like latches)
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21
picorv32.v
21
picorv32.v
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@ -597,13 +597,34 @@ module picorv32 #(
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if (instr_timer) new_ascii_instr = "timer";
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end
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reg [63:0] q_dbg_ascii_instr;
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reg [31:0] q_dbg_insn_imm;
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reg [31:0] q_dbg_insn_opcode;
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reg [4:0] q_dbg_insn_rs1;
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reg [4:0] q_dbg_insn_rs2;
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reg [4:0] q_dbg_insn_rd;
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always @(posedge clk) begin
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q_dbg_ascii_instr <= dbg_ascii_instr;
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q_dbg_insn_imm <= dbg_insn_imm;
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q_dbg_insn_opcode <= dbg_insn_opcode;
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q_dbg_insn_rs1 <= dbg_insn_rs1;
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q_dbg_insn_rs2 <= dbg_insn_rs2;
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q_dbg_insn_rd <= dbg_insn_rd;
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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dbg_insn_addr <= next_pc;
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end
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end
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always @* begin
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dbg_ascii_instr = q_dbg_ascii_instr;
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dbg_insn_imm = q_dbg_insn_imm;
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dbg_insn_opcode = q_dbg_insn_opcode;
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dbg_insn_rs1 = q_dbg_insn_rs1;
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dbg_insn_rs2 = q_dbg_insn_rs2;
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dbg_insn_rd = q_dbg_insn_rd;
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if (decoder_trigger_q && !decoder_pseudo_trigger_q) begin
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dbg_ascii_instr = new_ascii_instr;
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if (&mem_rdata_q[1:0])
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