mirror of https://github.com/YosysHQ/picorv32.git
scripts/icestorm: switch to nextpnr-ice40
nextpnr-ice40 gives a better fMAX for this design (by about ~9Mhz for me: ~59MHz -> ~68MHz) and is The Way Of The Future. Signed-off-by: Austin Seipp <aseipp@pobox.com>
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@ -15,11 +15,11 @@ firmware.bin: firmware.elf
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firmware.hex: firmware.bin
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firmware.hex: firmware.bin
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python3 ../../firmware/makehex.py $< 128 > $@
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python3 ../../firmware/makehex.py $< 128 > $@
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synth.blif: example.v ../../picorv32.v firmware.hex
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synth.json: example.v ../../picorv32.v firmware.hex
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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example.asc: synth.blif example.pcf
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example.asc: synth.json example.pcf
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arachne-pnr -d 8k -o $@ -p example.pcf $<
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nextpnr-ice40 --hx8k --package ct256 --json $< --pcf example.pcf --asc $@
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example.bin: example.asc
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example.bin: example.asc
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icepack $< $@
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icepack $< $@
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@ -34,7 +34,7 @@ example_sim: example_tb.vvp
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example_sim_vcd: example_tb.vvp
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example_sim_vcd: example_tb.vvp
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vvp -N $< +vcd
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vvp -N $< +vcd
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synth_tb.vvp: example_tb.v synth.blif
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synth_tb.vvp: example_tb.v synth.json
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iverilog -o $@ -s testbench synth.v example_tb.v `yosys-config --datdir/ice40/cells_sim.v`
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iverilog -o $@ -s testbench synth.v example_tb.v `yosys-config --datdir/ice40/cells_sim.v`
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chmod -x $@
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chmod -x $@
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@ -65,7 +65,7 @@ view: example.vcd
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clean:
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clean:
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f synth.log synth.v synth.blif route.v example.asc example.bin
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rm -f synth.log synth.v synth.json route.v example.asc example.bin
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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.PHONY: all prog_sram view clean
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.PHONY: all prog_sram view clean
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