2 Commits

Author	SHA1	Message	Date
Olof Kindgren	cd5d341e89	Add option to load alternative firmware with plusarg	2016-02-18 22:47:58 +01:00
Olof Kindgren	9591ae9f7d	Split out verilator-incompatible code to top-level testbench ... Verilator doesn't handle verilog code that deals with time, such as delayed signals or the repeat task. Clock and reset generation are therefore moved to a separate file that can be replaced by a verilator module. VCD generation is also affected by this.	2016-02-18 22:47:15 +01:00