mirror of https://github.com/YosysHQ/picorv32.git
141 lines
3.2 KiB
Verilog
141 lines
3.2 KiB
Verilog
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module top_small (
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input clk, resetn,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata
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);
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.LATCHED_MEM_RDATA(1),
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.TWO_STAGE_SHIFT(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0)
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) picorv32 (
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.clk (clk ),
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.resetn (resetn ),
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.mem_valid(mem_valid),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata)
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);
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endmodule
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module top_regular (
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input clk, resetn,
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output trap,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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output mem_la_write,
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output [31:0] mem_la_addr,
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output [31:0] mem_la_wdata,
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output [ 3:0] mem_la_wstrb
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);
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picorv32 picorv32 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read (mem_la_read ),
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr ),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_wstrb(mem_la_wstrb)
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);
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endmodule
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module top_large (
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input clk, resetn,
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output trap,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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output mem_la_write,
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output [31:0] mem_la_addr,
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output [31:0] mem_la_wdata,
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output [ 3:0] mem_la_wstrb,
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// Pico Co-Processor Interface (PCPI)
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output pcpi_valid,
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output [31:0] pcpi_insn,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs2,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready,
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// IRQ Interface
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input [31:0] irq,
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output [31:0] eoi
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);
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picorv32 #(
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.COMPRESSED_ISA(1),
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.BARREL_SHIFTER(1),
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.ENABLE_PCPI(1),
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.ENABLE_MUL(1),
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.ENABLE_IRQ(1)
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) picorv32 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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.mem_la_read (mem_la_read ),
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.mem_la_write (mem_la_write ),
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.mem_la_addr (mem_la_addr ),
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.mem_la_wdata (mem_la_wdata ),
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.mem_la_wstrb (mem_la_wstrb ),
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.pcpi_valid (pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_wr ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready (pcpi_ready ),
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.irq (irq ),
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.eoi (eoi )
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);
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endmodule
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