mirror of https://github.com/YosysHQ/picorv32.git
88 lines
1.9 KiB
Verilog
88 lines
1.9 KiB
Verilog
module testbench(input clk, mem_ready_0, mem_ready_1);
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reg resetn = 0;
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always @(posedge clk)
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resetn <= 1;
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reg pcpi_valid_0 = 1;
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reg pcpi_valid_1 = 1;
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wire [31:0] pcpi_insn = $anyconst;
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wire [31:0] pcpi_rs1 = $anyconst;
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wire [31:0] pcpi_rs2 = $anyconst;
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wire pcpi_wr_0;
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wire [31:0] pcpi_rd_0;
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wire pcpi_wait_0;
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wire pcpi_ready_0;
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wire pcpi_wr_1;
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wire [31:0] pcpi_rd_1;
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wire pcpi_wait_1;
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wire pcpi_ready_1;
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reg pcpi_wr_ref;
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reg [31:0] pcpi_rd_ref;
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reg pcpi_ready_ref = 0;
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picorv32_pcpi_mul mul_0 (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid_0),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_wr_0 ),
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.pcpi_rd (pcpi_rd_0 ),
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.pcpi_wait (pcpi_wait_0 ),
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.pcpi_ready(pcpi_ready_0),
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);
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picorv32_pcpi_fast_mul mul_1 (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid_1),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_wr_1 ),
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.pcpi_rd (pcpi_rd_1 ),
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.pcpi_wait (pcpi_wait_1 ),
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.pcpi_ready(pcpi_ready_1),
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);
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always @(posedge clk) begin
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if (resetn) begin
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if (pcpi_ready_0 && pcpi_ready_1) begin
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assert(pcpi_wr_0 == pcpi_wr_1);
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assert(pcpi_rd_0 == pcpi_rd_1);
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end
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if (pcpi_ready_0) begin
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pcpi_valid_0 <= 0;
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pcpi_wr_ref <= pcpi_wr_0;
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pcpi_rd_ref <= pcpi_rd_0;
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pcpi_ready_ref <= 1;
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if (pcpi_ready_ref) begin
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assert(pcpi_wr_0 == pcpi_wr_ref);
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assert(pcpi_rd_0 == pcpi_rd_ref);
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end
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end
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if (pcpi_ready_1) begin
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pcpi_valid_1 <= 0;
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pcpi_wr_ref <= pcpi_wr_1;
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pcpi_rd_ref <= pcpi_rd_1;
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pcpi_ready_ref <= 1;
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if (pcpi_ready_ref) begin
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assert(pcpi_wr_1 == pcpi_wr_ref);
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assert(pcpi_rd_1 == pcpi_rd_ref);
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end
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end
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end
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end
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endmodule
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