mirror of https://github.com/YosysHQ/picorv32.git
68 lines
1.7 KiB
Verilog
68 lines
1.7 KiB
Verilog
module testbench(input clk, mem_ready);
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`include "opcode.v"
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reg resetn = 0;
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always @(posedge clk) resetn <= 1;
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(* keep *) wire trap, mem_valid, mem_instr;
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(* keep *) wire [3:0] mem_wstrb;
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(* keep *) wire [31:0] mem_addr, mem_wdata, mem_rdata;
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(* keep *) wire [35:0] trace_data;
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reg [31:0] mem [0:2**30-1];
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assign mem_rdata = mem[mem_addr >> 2];
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always @(posedge clk) begin
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if (resetn && mem_valid && mem_ready) begin
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if (mem_wstrb[3]) mem[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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if (mem_wstrb[2]) mem[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[1]) mem[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[0]) mem[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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end
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end
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reg [1:0] mem_ready_stall = 0;
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always @(posedge clk) begin
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mem_ready_stall <= {mem_ready_stall, mem_valid && !mem_ready};
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restrict(&mem_ready_stall == 0);
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if (mem_instr && mem_ready && mem_valid) begin
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assume(opcode_valid(mem_rdata));
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assume(!opcode_branch(mem_rdata));
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assume(!opcode_load(mem_rdata));
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assume(!opcode_store(mem_rdata));
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end
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if (!mem_valid)
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assume(!mem_ready);
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if (resetn)
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assert(!trap);
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end
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picorv32 #(
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// change this settings as you like
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.ENABLE_REGS_DUALPORT(1),
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.TWO_STAGE_SHIFT(1),
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.BARREL_SHIFTER(0),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.ENABLE_MUL(0),
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.ENABLE_DIV(0)
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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endmodule
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