mirror of https://github.com/YosysHQ/picorv32.git
136 lines
3.5 KiB
Verilog
136 lines
3.5 KiB
Verilog
// Based on the benchmark from 2016 Yosys-SMTBMC presentation, which in turn is
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// based on the tracecmp2 test from this directory.
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module testbench (
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input clk,
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input [31:0] mem_rdata_in,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready
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);
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reg resetn = 0;
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always @(posedge clk)
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resetn <= 1;
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wire cpu0_trap;
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wire cpu0_mem_valid;
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wire cpu0_mem_instr;
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wire cpu0_mem_ready;
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wire [31:0] cpu0_mem_addr;
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wire [31:0] cpu0_mem_wdata;
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wire [3:0] cpu0_mem_wstrb;
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wire [31:0] cpu0_mem_rdata;
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wire cpu0_trace_valid;
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wire [35:0] cpu0_trace_data;
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wire cpu1_trap;
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wire cpu1_mem_valid;
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wire cpu1_mem_instr;
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wire cpu1_mem_ready;
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wire [31:0] cpu1_mem_addr;
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wire [31:0] cpu1_mem_wdata;
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wire [3:0] cpu1_mem_wstrb;
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wire [31:0] cpu1_mem_rdata;
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wire cpu1_trace_valid;
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wire [35:0] cpu1_trace_data;
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wire mem_ready;
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wire [31:0] mem_rdata;
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assign mem_ready = cpu0_mem_valid && cpu1_mem_valid;
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assign mem_rdata = mem_rdata_in;
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assign cpu0_mem_ready = mem_ready;
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assign cpu0_mem_rdata = mem_rdata;
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assign cpu1_mem_ready = mem_ready;
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assign cpu1_mem_rdata = mem_rdata;
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reg [ 2:0] trace_balance = 3'b010;
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reg [35:0] trace_buffer_cpu0 = 0, trace_buffer_cpu1 = 0;
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always @(posedge clk) begin
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if (resetn) begin
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if (cpu0_trace_valid)
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trace_buffer_cpu0 <= cpu0_trace_data;
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if (cpu1_trace_valid)
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trace_buffer_cpu1 <= cpu1_trace_data;
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if (cpu0_trace_valid && !cpu1_trace_valid)
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trace_balance <= trace_balance << 1;
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if (!cpu0_trace_valid && cpu1_trace_valid)
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trace_balance <= trace_balance >> 1;
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end
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end
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always @* begin
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if (resetn && cpu0_mem_ready) begin
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assert(cpu0_mem_addr == cpu1_mem_addr);
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assert(cpu0_mem_wstrb == cpu1_mem_wstrb);
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if (cpu0_mem_wstrb[3]) assert(cpu0_mem_wdata[31:24] == cpu1_mem_wdata[31:24]);
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if (cpu0_mem_wstrb[2]) assert(cpu0_mem_wdata[23:16] == cpu1_mem_wdata[23:16]);
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if (cpu0_mem_wstrb[1]) assert(cpu0_mem_wdata[15: 8] == cpu1_mem_wdata[15: 8]);
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if (cpu0_mem_wstrb[0]) assert(cpu0_mem_wdata[ 7: 0] == cpu1_mem_wdata[ 7: 0]);
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end
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if (trace_balance == 3'b010) begin
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assert(trace_buffer_cpu0 == trace_buffer_cpu1);
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end
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end
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.REGS_INIT_ZERO(1),
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.COMPRESSED_ISA(1),
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.ENABLE_TRACE(1),
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.TWO_STAGE_SHIFT(0),
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.ENABLE_PCPI(1)
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) cpu0 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (cpu0_trap ),
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.mem_valid (cpu0_mem_valid ),
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.mem_instr (cpu0_mem_instr ),
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.mem_ready (cpu0_mem_ready ),
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.mem_addr (cpu0_mem_addr ),
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.mem_wdata (cpu0_mem_wdata ),
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.mem_wstrb (cpu0_mem_wstrb ),
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.mem_rdata (cpu0_mem_rdata ),
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.pcpi_wr (pcpi_wr ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready (pcpi_ready ),
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.trace_valid (cpu0_trace_valid),
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.trace_data (cpu0_trace_data )
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);
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.REGS_INIT_ZERO(1),
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.COMPRESSED_ISA(1),
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.ENABLE_TRACE(1),
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.TWO_STAGE_SHIFT(1),
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.TWO_CYCLE_COMPARE(1),
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.TWO_CYCLE_ALU(1)
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) cpu1 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (cpu1_trap ),
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.mem_valid (cpu1_mem_valid ),
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.mem_instr (cpu1_mem_instr ),
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.mem_ready (cpu1_mem_ready ),
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.mem_addr (cpu1_mem_addr ),
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.mem_wdata (cpu1_mem_wdata ),
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.mem_wstrb (cpu1_mem_wstrb ),
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.mem_rdata (cpu1_mem_rdata ),
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.trace_valid (cpu1_trace_valid),
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.trace_data (cpu1_trace_data )
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);
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endmodule
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