mirror of https://github.com/YosysHQ/picorv32.git
1368 lines
42 KiB
Verilog
1368 lines
42 KiB
Verilog
/*
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* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
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*
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* Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`timescale 1 ns / 1 ps
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// `define DEBUG
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/***************************************************************
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* picorv32
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***************************************************************/
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module picorv32 #(
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parameter [ 0:0] ENABLE_COUNTERS = 1,
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] CATCH_MISALIGN = 1,
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
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) (
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input clk, resetn,
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output reg trap,
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output reg mem_valid,
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output reg mem_instr,
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input mem_ready,
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output reg [31:0] mem_addr,
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output reg [31:0] mem_wdata,
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output reg [ 3:0] mem_wstrb,
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input [31:0] mem_rdata,
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// Look-Ahead Interface
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output mem_la_read,
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output mem_la_write,
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output [31:0] mem_la_addr,
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output reg [31:0] mem_la_wdata,
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output reg [ 3:0] mem_la_wstrb,
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// Pico Co-Processor Interface (PCPI)
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output reg pcpi_valid,
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output reg [31:0] pcpi_insn,
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output [31:0] pcpi_rs1,
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output [31:0] pcpi_rs2,
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input pcpi_wr,
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input [31:0] pcpi_rd,
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input pcpi_wait,
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input pcpi_ready,
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// IRQ Interface
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input [31:0] irq,
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output reg [31:0] eoi
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);
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localparam integer irq_timer = 0;
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localparam integer irq_sbreak = 1;
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localparam integer irq_buserror = 2;
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localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
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localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
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localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
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localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL;
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reg [63:0] count_cycle, count_instr;
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reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out, reg_alu_out;
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reg [31:0] cpuregs [0:regfile_size-1];
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reg [4:0] reg_sh;
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assign pcpi_rs1 = reg_op1;
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assign pcpi_rs2 = reg_op2;
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wire [31:0] next_pc;
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reg irq_active;
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reg [31:0] irq_mask;
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reg [31:0] irq_pending;
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reg [31:0] timer;
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// Internal PCPI Cores
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wire pcpi_mul_wr;
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wire [31:0] pcpi_mul_rd;
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wire pcpi_mul_wait;
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wire pcpi_mul_ready;
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reg pcpi_int_wr;
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reg [31:0] pcpi_int_rd;
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reg pcpi_int_wait;
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reg pcpi_int_ready;
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generate if (ENABLE_MUL) begin
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_mul_wr ),
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.pcpi_rd (pcpi_mul_rd ),
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.pcpi_wait (pcpi_mul_wait ),
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.pcpi_ready(pcpi_mul_ready )
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);
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end else begin
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assign pcpi_mul_wr = 0;
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assign pcpi_mul_rd = 1'bx;
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assign pcpi_mul_wait = 0;
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assign pcpi_mul_ready = 0;
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end endgenerate
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always @* begin
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pcpi_int_wr = 0;
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pcpi_int_rd = 1'bx;
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pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, ENABLE_MUL && pcpi_mul_wait};
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pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, ENABLE_MUL && pcpi_mul_ready};
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(* parallel_case *)
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case (1'b1)
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ENABLE_PCPI && pcpi_ready: begin
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pcpi_int_wr = pcpi_wr;
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pcpi_int_rd = pcpi_rd;
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end
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ENABLE_MUL && pcpi_mul_ready: begin
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pcpi_int_wr = pcpi_mul_wr;
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pcpi_int_rd = pcpi_mul_rd;
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end
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endcase
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end
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// Memory Interface
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reg [1:0] mem_state;
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reg [1:0] mem_wordsize;
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reg [31:0] mem_rdata_word;
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reg [31:0] mem_rdata_q;
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reg mem_do_prefetch;
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reg mem_do_rinst;
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reg mem_do_rdata;
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reg mem_do_wdata;
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wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
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wire mem_done = (mem_ready && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst);
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assign mem_la_write = resetn && !mem_state && mem_do_wdata;
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assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);
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assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? next_pc : {reg_op1[31:2], 2'b00};
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wire [31:0] mem_rdata_latched;
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assign mem_rdata_latched = ((mem_valid && mem_ready) || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
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always @* begin
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(* full_case *)
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case (mem_wordsize)
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0: begin
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mem_la_wdata = reg_op2;
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mem_la_wstrb = 4'b1111;
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mem_rdata_word = mem_rdata;
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end
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1: begin
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mem_la_wdata = {2{reg_op2[15:0]}};
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mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
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case (reg_op1[1])
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1'b0: mem_rdata_word = mem_rdata[15: 0];
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1'b1: mem_rdata_word = mem_rdata[31:16];
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endcase
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end
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2: begin
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mem_la_wdata = {4{reg_op2[7:0]}};
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mem_la_wstrb = 4'b0001 << reg_op1[1:0];
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case (reg_op1[1:0])
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2'b00: mem_rdata_word = mem_rdata[ 7: 0];
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2'b01: mem_rdata_word = mem_rdata[15: 8];
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2'b10: mem_rdata_word = mem_rdata[23:16];
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2'b11: mem_rdata_word = mem_rdata[31:24];
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endcase
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end
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endcase
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end
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always @(posedge clk) begin
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if (mem_valid && mem_ready)
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mem_rdata_q <= mem_rdata_latched;
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end
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always @(posedge clk) begin
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if (!resetn) begin
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mem_state <= 0;
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mem_valid <= 0;
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end else case (mem_state)
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0: begin
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mem_addr <= mem_la_addr;
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mem_wdata <= mem_la_wdata;
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mem_wstrb <= mem_la_wstrb;
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if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
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mem_valid <= 1;
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mem_instr <= mem_do_prefetch || mem_do_rinst;
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mem_wstrb <= 0;
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mem_state <= 1;
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end
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if (mem_do_wdata) begin
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mem_valid <= 1;
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mem_instr <= 0;
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mem_state <= 2;
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end
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end
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1: begin
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if (mem_ready) begin
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mem_valid <= 0;
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mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
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end
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end
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2: begin
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if (mem_ready) begin
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mem_valid <= 0;
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mem_state <= 0;
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end
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end
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3: begin
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if (mem_do_rinst) begin
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mem_state <= 0;
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end
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end
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endcase
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end
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// Instruction Decoder
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reg instr_lui, instr_auipc, instr_jal, instr_jalr;
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reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
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reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
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reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
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reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
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reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh;
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reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
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wire instr_trap;
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reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
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reg [31:0] decoded_imm, decoded_imm_uj;
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reg decoder_trigger;
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reg decoder_trigger_q;
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reg decoder_pseudo_trigger;
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reg is_lui_auipc_jal;
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reg is_lb_lh_lw_lbu_lhu;
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reg is_slli_srli_srai;
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reg is_jalr_addi_slti_sltiu_xori_ori_andi;
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reg is_sb_sh_sw;
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reg is_sll_srl_sra;
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reg is_lui_auipc_jal_jalr_addi_add;
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reg is_slti_blt_slt;
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reg is_sltiu_bltu_sltu;
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reg is_beq_bne_blt_bge_bltu_bgeu;
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reg is_lbu_lhu_lw;
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reg is_alu_reg_imm;
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reg is_alu_reg_reg;
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reg is_compare;
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assign instr_trap = (CATCH_ILLINSN || ENABLE_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
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instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
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instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
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instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
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instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
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instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
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instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
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wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
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assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
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reg [63:0] new_instruction;
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reg [63:0] instruction;
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always @* begin
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new_instruction = "";
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if (instr_lui) new_instruction = "lui";
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if (instr_auipc) new_instruction = "auipc";
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if (instr_jal) new_instruction = "jal";
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if (instr_jalr) new_instruction = "jalr";
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if (instr_beq) new_instruction = "beq";
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if (instr_bne) new_instruction = "bne";
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if (instr_blt) new_instruction = "blt";
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if (instr_bge) new_instruction = "bge";
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if (instr_bltu) new_instruction = "bltu";
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if (instr_bgeu) new_instruction = "bgeu";
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if (instr_lb) new_instruction = "lb";
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if (instr_lh) new_instruction = "lh";
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if (instr_lw) new_instruction = "lw";
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if (instr_lbu) new_instruction = "lbu";
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if (instr_lhu) new_instruction = "lhu";
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if (instr_sb) new_instruction = "sb";
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if (instr_sh) new_instruction = "sh";
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if (instr_sw) new_instruction = "sw";
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if (instr_addi) new_instruction = "addi";
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if (instr_slti) new_instruction = "slti";
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if (instr_sltiu) new_instruction = "sltiu";
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if (instr_xori) new_instruction = "xori";
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if (instr_ori) new_instruction = "ori";
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if (instr_andi) new_instruction = "andi";
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if (instr_slli) new_instruction = "slli";
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if (instr_srli) new_instruction = "srli";
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if (instr_srai) new_instruction = "srai";
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if (instr_add) new_instruction = "add";
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if (instr_sub) new_instruction = "sub";
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if (instr_sll) new_instruction = "sll";
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if (instr_slt) new_instruction = "slt";
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if (instr_sltu) new_instruction = "sltu";
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if (instr_xor) new_instruction = "xor";
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if (instr_srl) new_instruction = "srl";
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if (instr_sra) new_instruction = "sra";
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if (instr_or) new_instruction = "or";
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if (instr_and) new_instruction = "and";
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if (instr_rdcycle) new_instruction = "rdcycle";
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if (instr_rdcycleh) new_instruction = "rdcycleh";
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if (instr_rdinstr) new_instruction = "rdinstr";
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if (instr_rdinstrh) new_instruction = "rdinstrh";
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if (instr_getq) new_instruction = "getq";
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if (instr_setq) new_instruction = "setq";
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if (instr_retirq) new_instruction = "retirq";
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if (instr_maskirq) new_instruction = "maskirq";
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if (instr_waitirq) new_instruction = "waitirq";
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if (instr_timer) new_instruction = "timer";
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if (decoder_trigger_q)
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instruction = new_instruction;
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end
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always @(posedge clk) begin
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is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
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is_lui_auipc_jal_jalr_addi_add <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add};
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is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
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is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
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is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
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is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
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if (mem_do_rinst && mem_done) begin
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instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
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instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
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instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111;
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instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
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instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
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is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
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is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
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is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
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is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
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is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
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{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
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decoded_rd <= mem_rdata_latched[11:7];
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decoded_rs1 <= mem_rdata_latched[19:15];
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decoded_rs2 <= mem_rdata_latched[24:20];
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if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
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decoded_rs1[regindex_bits-1] <= 1; // instr_getq
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if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
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decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
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end
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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if (WITH_PCPI) begin
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pcpi_insn <= mem_rdata_q;
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end
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instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
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instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
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instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
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instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
|
|
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
|
|
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
|
|
|
|
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
|
|
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
|
|
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
|
|
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
|
|
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
|
|
|
|
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
|
|
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
|
|
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
|
|
|
|
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
|
|
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
|
|
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
|
|
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
|
|
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
|
|
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
|
|
|
|
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
|
|
|
|
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
|
|
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
|
|
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
|
|
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
|
|
|
|
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
|
|
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
|
|
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
|
|
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS;
|
|
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
|
|
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS;
|
|
|
|
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
|
|
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
|
|
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
|
|
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
|
|
|
|
is_slli_srli_srai <= is_alu_reg_imm && |{
|
|
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
|
|
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
|
|
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
|
|
};
|
|
|
|
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
|
|
mem_rdata_q[14:12] == 3'b000,
|
|
mem_rdata_q[14:12] == 3'b010,
|
|
mem_rdata_q[14:12] == 3'b011,
|
|
mem_rdata_q[14:12] == 3'b100,
|
|
mem_rdata_q[14:12] == 3'b110,
|
|
mem_rdata_q[14:12] == 3'b111
|
|
};
|
|
|
|
is_sll_srl_sra <= is_alu_reg_reg && |{
|
|
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
|
|
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
|
|
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
|
|
};
|
|
|
|
(* parallel_case *)
|
|
case (1'b1)
|
|
instr_jal:
|
|
decoded_imm <= decoded_imm_uj;
|
|
|{instr_lui, instr_auipc}:
|
|
decoded_imm <= mem_rdata_q[31:12] << 12;
|
|
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
|
|
decoded_imm <= $signed(mem_rdata_q[31:20]);
|
|
is_beq_bne_blt_bge_bltu_bgeu:
|
|
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
|
|
is_sb_sh_sw:
|
|
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
|
|
default:
|
|
decoded_imm <= 1'bx;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
// Main State Machine
|
|
|
|
localparam cpu_state_trap = 8'b10000000;
|
|
localparam cpu_state_fetch = 8'b01000000;
|
|
localparam cpu_state_ld_rs1 = 8'b00100000;
|
|
localparam cpu_state_ld_rs2 = 8'b00010000;
|
|
localparam cpu_state_exec = 8'b00001000;
|
|
localparam cpu_state_shift = 8'b00000100;
|
|
localparam cpu_state_stmem = 8'b00000010;
|
|
localparam cpu_state_ldmem = 8'b00000001;
|
|
|
|
reg [7:0] cpu_state;
|
|
reg [1:0] irq_state;
|
|
|
|
reg set_mem_do_rinst;
|
|
reg set_mem_do_rdata;
|
|
reg set_mem_do_wdata;
|
|
|
|
reg latched_store;
|
|
reg latched_stalu;
|
|
reg latched_branch;
|
|
reg latched_is_lu;
|
|
reg latched_is_lh;
|
|
reg latched_is_lb;
|
|
reg [regindex_bits-1:0] latched_rd;
|
|
|
|
reg [31:0] current_pc;
|
|
assign next_pc = latched_store && latched_branch ? reg_out : reg_next_pc;
|
|
|
|
reg [3:0] pcpi_timeout_counter;
|
|
reg pcpi_timeout;
|
|
|
|
reg [31:0] next_irq_pending;
|
|
reg do_waitirq;
|
|
|
|
reg [31:0] alu_out;
|
|
reg alu_out_0;
|
|
|
|
always @* begin
|
|
alu_out_0 = 'bx;
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
instr_beq:
|
|
alu_out_0 = reg_op1 == reg_op2;
|
|
instr_bne:
|
|
alu_out_0 = reg_op1 != reg_op2;
|
|
instr_bge:
|
|
alu_out_0 = $signed(reg_op1) >= $signed(reg_op2);
|
|
instr_bgeu:
|
|
alu_out_0 = reg_op1 >= reg_op2;
|
|
is_slti_blt_slt:
|
|
alu_out_0 = $signed(reg_op1) < $signed(reg_op2);
|
|
is_sltiu_bltu_sltu:
|
|
alu_out_0 = reg_op1 < reg_op2;
|
|
endcase
|
|
|
|
alu_out = 'bx;
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
is_lui_auipc_jal_jalr_addi_add:
|
|
alu_out = reg_op1 + reg_op2;
|
|
instr_sub:
|
|
alu_out = reg_op1 - reg_op2;
|
|
is_compare:
|
|
alu_out = alu_out_0;
|
|
instr_xori || instr_xor:
|
|
alu_out = reg_op1 ^ reg_op2;
|
|
instr_ori || instr_or:
|
|
alu_out = reg_op1 | reg_op2;
|
|
instr_andi || instr_and:
|
|
alu_out = reg_op1 & reg_op2;
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
trap <= 0;
|
|
reg_sh <= 'bx;
|
|
reg_out <= 'bx;
|
|
set_mem_do_rinst = 0;
|
|
set_mem_do_rdata = 0;
|
|
set_mem_do_wdata = 0;
|
|
|
|
reg_alu_out <= alu_out;
|
|
|
|
if (WITH_PCPI && CATCH_ILLINSN) begin
|
|
if (resetn && pcpi_valid && !pcpi_int_wait) begin
|
|
if (pcpi_timeout_counter)
|
|
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
|
|
end else
|
|
pcpi_timeout_counter <= ~0;
|
|
pcpi_timeout <= !pcpi_timeout_counter;
|
|
end
|
|
|
|
if (ENABLE_COUNTERS)
|
|
count_cycle <= resetn ? count_cycle + 1 : 0;
|
|
|
|
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
|
|
|
|
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
|
|
if (timer - 1 == 0)
|
|
next_irq_pending[irq_timer] = 1;
|
|
timer <= timer - 1;
|
|
end
|
|
|
|
if (ENABLE_IRQ) begin
|
|
next_irq_pending = next_irq_pending | irq;
|
|
end
|
|
|
|
decoder_trigger_q <= decoder_trigger;
|
|
decoder_trigger <= mem_do_rinst && mem_done;
|
|
decoder_pseudo_trigger <= 0;
|
|
do_waitirq <= 0;
|
|
|
|
if (!resetn) begin
|
|
reg_pc <= PROGADDR_RESET;
|
|
reg_next_pc <= PROGADDR_RESET;
|
|
if (ENABLE_COUNTERS)
|
|
count_instr <= 0;
|
|
latched_store <= 0;
|
|
latched_stalu <= 0;
|
|
latched_branch <= 0;
|
|
latched_is_lu <= 0;
|
|
latched_is_lh <= 0;
|
|
latched_is_lb <= 0;
|
|
pcpi_valid <= 0;
|
|
irq_active <= 0;
|
|
irq_mask <= ~0;
|
|
next_irq_pending = 0;
|
|
irq_state <= 0;
|
|
eoi <= 0;
|
|
timer <= 0;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
(* parallel_case, full_case *)
|
|
case (cpu_state)
|
|
cpu_state_trap: begin
|
|
trap <= 1;
|
|
end
|
|
cpu_state_fetch: begin
|
|
mem_do_rinst <= !decoder_trigger && !do_waitirq;
|
|
mem_wordsize <= 0;
|
|
|
|
current_pc = reg_next_pc;
|
|
|
|
if (latched_branch) begin
|
|
current_pc = latched_store ? (latched_stalu ? reg_alu_out : reg_out) : reg_next_pc;
|
|
`ifdef DEBUG
|
|
$display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);
|
|
`endif
|
|
cpuregs[latched_rd] <= reg_pc + 4;
|
|
end else
|
|
if (latched_store) begin
|
|
`ifdef DEBUG
|
|
$display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? reg_alu_out : reg_out);
|
|
`endif
|
|
cpuregs[latched_rd] <= latched_stalu ? reg_alu_out : reg_out;
|
|
end else
|
|
if (ENABLE_IRQ && irq_state[0]) begin
|
|
cpuregs[latched_rd] <= current_pc;
|
|
current_pc = PROGADDR_IRQ;
|
|
irq_active <= 1;
|
|
mem_do_rinst <= 1;
|
|
end else
|
|
if (ENABLE_IRQ && irq_state[1]) begin
|
|
eoi <= irq_pending & ~irq_mask;
|
|
cpuregs[latched_rd] <= irq_pending & ~irq_mask;
|
|
next_irq_pending = next_irq_pending & irq_mask;
|
|
end
|
|
|
|
reg_pc <= current_pc;
|
|
reg_next_pc <= current_pc;
|
|
|
|
latched_store <= 0;
|
|
latched_stalu <= 0;
|
|
latched_branch <= 0;
|
|
latched_is_lu <= 0;
|
|
latched_is_lh <= 0;
|
|
latched_is_lb <= 0;
|
|
latched_rd <= decoded_rd;
|
|
|
|
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && |(irq_pending & ~irq_mask)) || irq_state)) begin
|
|
irq_state <=
|
|
irq_state == 2'b00 ? 2'b01 :
|
|
irq_state == 2'b01 ? 2'b10 : 2'b00;
|
|
if (ENABLE_IRQ_QREGS)
|
|
latched_rd <= irqregs_offset | irq_state[0];
|
|
else
|
|
latched_rd <= irq_state[0] ? 4 : 3;
|
|
end else
|
|
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
|
|
if (irq_pending) begin
|
|
latched_store <= 1;
|
|
reg_out <= irq_pending;
|
|
reg_next_pc <= current_pc + 4;
|
|
mem_do_rinst <= 1;
|
|
end else
|
|
do_waitirq <= 1;
|
|
end else
|
|
if (decoder_trigger) begin
|
|
`ifdef DEBUG
|
|
$display("-- %-0t", $time);
|
|
`endif
|
|
reg_next_pc <= current_pc + 4;
|
|
if (ENABLE_COUNTERS)
|
|
count_instr <= count_instr + 1;
|
|
if (instr_jal) begin
|
|
`ifdef DEBUG
|
|
$display("DECODE: 0x%08x jal", current_pc);
|
|
`endif
|
|
mem_do_rinst <= 1;
|
|
reg_next_pc <= current_pc + decoded_imm_uj;
|
|
latched_branch <= 1;
|
|
end else begin
|
|
mem_do_rinst <= 0;
|
|
mem_do_prefetch <= !instr_jalr && !instr_retirq;
|
|
cpu_state <= cpu_state_ld_rs1;
|
|
end
|
|
end
|
|
end
|
|
cpu_state_ld_rs1: begin
|
|
reg_op1 <= 'bx;
|
|
reg_op2 <= 'bx;
|
|
`ifdef DEBUG
|
|
$display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");
|
|
`endif
|
|
if ((CATCH_ILLINSN || WITH_PCPI) && instr_trap) begin
|
|
if (WITH_PCPI) begin
|
|
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
|
|
if (ENABLE_REGS_DUALPORT) begin
|
|
pcpi_valid <= 1;
|
|
reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
|
|
reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
|
|
if (pcpi_int_ready) begin
|
|
mem_do_rinst <= 1;
|
|
pcpi_valid <= 0;
|
|
reg_out <= pcpi_int_rd;
|
|
latched_store <= pcpi_int_wr;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (CATCH_ILLINSN && pcpi_timeout) begin
|
|
`ifdef DEBUG
|
|
$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
|
|
`endif
|
|
if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
|
|
next_irq_pending[irq_sbreak] = 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
cpu_state <= cpu_state_trap;
|
|
end
|
|
end else begin
|
|
cpu_state <= cpu_state_ld_rs2;
|
|
end
|
|
end else begin
|
|
`ifdef DEBUG
|
|
$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
|
|
`endif
|
|
if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
|
|
next_irq_pending[irq_sbreak] = 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
cpu_state <= cpu_state_trap;
|
|
end
|
|
end else
|
|
if (is_rdcycle_rdcycleh_rdinstr_rdinstrh) begin
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
instr_rdcycle:
|
|
reg_out <= count_cycle[31:0];
|
|
instr_rdcycleh:
|
|
reg_out <= count_cycle[63:32];
|
|
instr_rdinstr:
|
|
reg_out <= count_instr[31:0];
|
|
instr_rdinstrh:
|
|
reg_out <= count_instr[63:32];
|
|
endcase
|
|
latched_store <= 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (is_lui_auipc_jal) begin
|
|
reg_op1 <= instr_lui ? 0 : reg_pc;
|
|
reg_op2 <= decoded_imm;
|
|
mem_do_rinst <= mem_do_prefetch;
|
|
cpu_state <= cpu_state_exec;
|
|
end else
|
|
if (ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq) begin
|
|
reg_out <= cpuregs[decoded_rs1];
|
|
latched_store <= 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq) begin
|
|
reg_out <= cpuregs[decoded_rs1];
|
|
latched_rd <= latched_rd | irqregs_offset;
|
|
latched_store <= 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (ENABLE_IRQ && instr_retirq) begin
|
|
eoi <= 0;
|
|
irq_active <= 0;
|
|
latched_branch <= 1;
|
|
latched_store <= 1;
|
|
reg_out <= cpuregs[decoded_rs1];
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (ENABLE_IRQ && instr_maskirq) begin
|
|
latched_store <= 1;
|
|
reg_out <= irq_mask;
|
|
irq_mask <= (decoded_rs1 ? cpuregs[decoded_rs1] : 0) | MASKED_IRQ;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer) begin
|
|
latched_store <= 1;
|
|
reg_out <= timer;
|
|
timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else begin
|
|
`ifdef DEBUG
|
|
$display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);
|
|
`endif
|
|
reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
|
|
if (is_lb_lh_lw_lbu_lhu) begin
|
|
cpu_state <= cpu_state_ldmem;
|
|
mem_do_rinst <= 1;
|
|
end else if (is_slli_srli_srai) begin
|
|
reg_sh <= decoded_rs2;
|
|
cpu_state <= cpu_state_shift;
|
|
end else if (is_jalr_addi_slti_sltiu_xori_ori_andi) begin
|
|
reg_op2 <= decoded_imm;
|
|
mem_do_rinst <= mem_do_prefetch;
|
|
cpu_state <= cpu_state_exec;
|
|
end else if (ENABLE_REGS_DUALPORT) begin
|
|
`ifdef DEBUG
|
|
$display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);
|
|
`endif
|
|
reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
|
|
reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
|
|
if (is_sb_sh_sw) begin
|
|
cpu_state <= cpu_state_stmem;
|
|
mem_do_rinst <= 1;
|
|
end else if (is_sll_srl_sra) begin
|
|
cpu_state <= cpu_state_shift;
|
|
end else begin
|
|
mem_do_rinst <= mem_do_prefetch;
|
|
cpu_state <= cpu_state_exec;
|
|
end
|
|
end else
|
|
cpu_state <= cpu_state_ld_rs2;
|
|
end
|
|
end
|
|
cpu_state_ld_rs2: begin
|
|
`ifdef DEBUG
|
|
$display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);
|
|
`endif
|
|
reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
|
|
reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
|
|
if (WITH_PCPI && instr_trap) begin
|
|
pcpi_valid <= 1;
|
|
if (pcpi_int_ready) begin
|
|
mem_do_rinst <= 1;
|
|
pcpi_valid <= 0;
|
|
reg_out <= pcpi_int_rd;
|
|
latched_store <= pcpi_int_wr;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
if (CATCH_ILLINSN && pcpi_timeout) begin
|
|
`ifdef DEBUG
|
|
$display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);
|
|
`endif
|
|
if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin
|
|
next_irq_pending[irq_sbreak] = 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else
|
|
cpu_state <= cpu_state_trap;
|
|
end
|
|
end else
|
|
if (is_sb_sh_sw) begin
|
|
cpu_state <= cpu_state_stmem;
|
|
mem_do_rinst <= 1;
|
|
end else if (is_sll_srl_sra) begin
|
|
cpu_state <= cpu_state_shift;
|
|
end else begin
|
|
mem_do_rinst <= mem_do_prefetch;
|
|
cpu_state <= cpu_state_exec;
|
|
end
|
|
end
|
|
cpu_state_exec: begin
|
|
latched_store <= alu_out_0;
|
|
latched_branch <= alu_out_0;
|
|
reg_out <= reg_pc + decoded_imm;
|
|
if (is_beq_bne_blt_bge_bltu_bgeu) begin
|
|
latched_rd <= 0;
|
|
if (mem_done)
|
|
cpu_state <= cpu_state_fetch;
|
|
if (alu_out_0) begin
|
|
decoder_trigger <= 0;
|
|
set_mem_do_rinst = 1;
|
|
end
|
|
end else begin
|
|
latched_branch <= instr_jalr;
|
|
latched_store <= 1;
|
|
latched_stalu <= 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end
|
|
end
|
|
cpu_state_shift: begin
|
|
latched_store <= 1;
|
|
if (reg_sh == 0) begin
|
|
reg_out <= reg_op1;
|
|
mem_do_rinst <= mem_do_prefetch;
|
|
cpu_state <= cpu_state_fetch;
|
|
end else if (reg_sh >= 4) begin
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
|
|
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
|
|
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
|
|
endcase
|
|
reg_sh <= reg_sh - 4;
|
|
end else begin
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
|
|
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
|
|
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
|
|
endcase
|
|
reg_sh <= reg_sh - 1;
|
|
end
|
|
end
|
|
cpu_state_stmem: begin
|
|
if (!mem_do_prefetch || mem_done) begin
|
|
if (!mem_do_wdata) begin
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
instr_sb: mem_wordsize <= 2;
|
|
instr_sh: mem_wordsize <= 1;
|
|
instr_sw: mem_wordsize <= 0;
|
|
endcase
|
|
reg_op1 <= reg_op1 + decoded_imm;
|
|
set_mem_do_wdata = 1;
|
|
end
|
|
if (!mem_do_prefetch && mem_done) begin
|
|
cpu_state <= cpu_state_fetch;
|
|
decoder_trigger <= 1;
|
|
decoder_pseudo_trigger <= 1;
|
|
end
|
|
end
|
|
end
|
|
cpu_state_ldmem: begin
|
|
latched_store <= 1;
|
|
if (!mem_do_prefetch || mem_done) begin
|
|
if (!mem_do_rdata) begin
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
instr_lb || instr_lbu: mem_wordsize <= 2;
|
|
instr_lh || instr_lhu: mem_wordsize <= 1;
|
|
instr_lw: mem_wordsize <= 0;
|
|
endcase
|
|
latched_is_lu <= is_lbu_lhu_lw;
|
|
latched_is_lh <= instr_lh;
|
|
latched_is_lb <= instr_lb;
|
|
reg_op1 <= reg_op1 + decoded_imm;
|
|
set_mem_do_rdata = 1;
|
|
end
|
|
if (!mem_do_prefetch && mem_done) begin
|
|
(* parallel_case, full_case *)
|
|
case (1'b1)
|
|
latched_is_lu: reg_out <= mem_rdata_word;
|
|
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
|
|
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
|
|
endcase
|
|
decoder_trigger <= 1;
|
|
decoder_pseudo_trigger <= 1;
|
|
cpu_state <= cpu_state_fetch;
|
|
end
|
|
end
|
|
end
|
|
endcase
|
|
|
|
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
|
|
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
|
|
`ifdef DEBUG
|
|
$display("MISALIGNED WORD: 0x%08x", reg_op1);
|
|
`endif
|
|
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
|
|
next_irq_pending[irq_buserror] = 1;
|
|
end else
|
|
cpu_state <= cpu_state_trap;
|
|
end
|
|
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
|
|
`ifdef DEBUG
|
|
$display("MISALIGNED HALFWORD: 0x%08x", reg_op1);
|
|
`endif
|
|
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
|
|
next_irq_pending[irq_buserror] = 1;
|
|
end else
|
|
cpu_state <= cpu_state_trap;
|
|
end
|
|
end
|
|
if (CATCH_MISALIGN && resetn && mem_do_rinst && reg_pc[1:0] != 0) begin
|
|
`ifdef DEBUG
|
|
$display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);
|
|
`endif
|
|
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
|
|
next_irq_pending[irq_buserror] = 1;
|
|
end else
|
|
cpu_state <= cpu_state_trap;
|
|
end
|
|
|
|
if (!resetn || mem_done) begin
|
|
mem_do_prefetch <= 0;
|
|
mem_do_rinst <= 0;
|
|
mem_do_rdata <= 0;
|
|
mem_do_wdata <= 0;
|
|
end
|
|
|
|
if (set_mem_do_rinst)
|
|
mem_do_rinst <= 1;
|
|
if (set_mem_do_rdata)
|
|
mem_do_rdata <= 1;
|
|
if (set_mem_do_wdata)
|
|
mem_do_wdata <= 1;
|
|
|
|
irq_pending <= next_irq_pending & ~MASKED_IRQ;
|
|
|
|
reg_pc[1:0] <= 0;
|
|
reg_next_pc[1:0] <= 0;
|
|
current_pc = 'bx;
|
|
end
|
|
endmodule
|
|
|
|
|
|
/***************************************************************
|
|
* picorv32_pcpi_mul
|
|
***************************************************************/
|
|
|
|
module picorv32_pcpi_mul #(
|
|
parameter STEPS_AT_ONCE = 1,
|
|
parameter CARRY_CHAIN = 4
|
|
) (
|
|
input clk, resetn,
|
|
|
|
input pcpi_valid,
|
|
input [31:0] pcpi_insn,
|
|
input [31:0] pcpi_rs1,
|
|
input [31:0] pcpi_rs2,
|
|
output reg pcpi_wr,
|
|
output reg [31:0] pcpi_rd,
|
|
output reg pcpi_wait,
|
|
output reg pcpi_ready
|
|
);
|
|
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
|
|
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
|
|
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
|
|
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
|
|
wire instr_rs2_signed = |{instr_mulh};
|
|
|
|
reg pcpi_wait_q;
|
|
wire mul_start = pcpi_wait && !pcpi_wait_q;
|
|
|
|
always @(posedge clk) begin
|
|
instr_mul <= 0;
|
|
instr_mulh <= 0;
|
|
instr_mulhsu <= 0;
|
|
instr_mulhu <= 0;
|
|
|
|
if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
|
|
case (pcpi_insn[14:12])
|
|
3'b000: instr_mul <= 1;
|
|
3'b001: instr_mulh <= 1;
|
|
3'b010: instr_mulhsu <= 1;
|
|
3'b011: instr_mulhu <= 1;
|
|
endcase
|
|
end
|
|
|
|
pcpi_wait <= instr_any_mul;
|
|
pcpi_wait_q <= pcpi_wait;
|
|
end
|
|
|
|
reg [63:0] rs1, rs2, rd, rdx;
|
|
reg [63:0] next_rs1, next_rs2, this_rs2;
|
|
reg [63:0] next_rd, next_rdx, next_rdt;
|
|
reg [6:0] mul_counter;
|
|
reg mul_waiting;
|
|
reg mul_finish;
|
|
integer i, j;
|
|
|
|
// carry save accumulator
|
|
always @* begin
|
|
next_rd = rd;
|
|
next_rdx = rdx;
|
|
next_rs1 = rs1;
|
|
next_rs2 = rs2;
|
|
|
|
for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
|
|
this_rs2 = next_rs1[0] ? next_rs2 : 0;
|
|
if (CARRY_CHAIN == 0) begin
|
|
next_rdt = next_rd ^ next_rdx ^ this_rs2;
|
|
next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
|
|
next_rd = next_rdt;
|
|
end else begin
|
|
next_rdt = 0;
|
|
for (j = 0; j < 64; j = j + CARRY_CHAIN)
|
|
{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
|
|
next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
|
|
next_rdx = next_rdt << 1;
|
|
end
|
|
next_rs1 = next_rs1 >> 1;
|
|
next_rs2 = next_rs2 << 1;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
mul_finish <= 0;
|
|
if (!resetn) begin
|
|
mul_waiting <= 1;
|
|
end else
|
|
if (mul_waiting) begin
|
|
if (instr_rs1_signed)
|
|
rs1 <= $signed(pcpi_rs1);
|
|
else
|
|
rs1 <= $unsigned(pcpi_rs1);
|
|
|
|
if (instr_rs2_signed)
|
|
rs2 <= $signed(pcpi_rs2);
|
|
else
|
|
rs2 <= $unsigned(pcpi_rs2);
|
|
|
|
rd <= 0;
|
|
rdx <= 0;
|
|
mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
|
|
mul_waiting <= !mul_start;
|
|
end else begin
|
|
rd <= next_rd;
|
|
rdx <= next_rdx;
|
|
rs1 <= next_rs1;
|
|
rs2 <= next_rs2;
|
|
|
|
mul_counter <= mul_counter - STEPS_AT_ONCE;
|
|
if (mul_counter[6]) begin
|
|
mul_finish <= 1;
|
|
mul_waiting <= 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
pcpi_wr <= 0;
|
|
pcpi_ready <= 0;
|
|
if (mul_finish) begin
|
|
pcpi_wr <= 1;
|
|
pcpi_ready <= 1;
|
|
pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
|
|
/***************************************************************
|
|
* picorv32_axi
|
|
***************************************************************/
|
|
|
|
module picorv32_axi #(
|
|
parameter [ 0:0] ENABLE_COUNTERS = 1,
|
|
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
|
|
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
|
|
parameter [ 0:0] CATCH_MISALIGN = 1,
|
|
parameter [ 0:0] CATCH_ILLINSN = 1,
|
|
parameter [ 0:0] ENABLE_PCPI = 0,
|
|
parameter [ 0:0] ENABLE_MUL = 0,
|
|
parameter [ 0:0] ENABLE_IRQ = 0,
|
|
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
|
|
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
|
|
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
|
|
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
|
|
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
|
|
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
|
|
) (
|
|
input clk, resetn,
|
|
output trap,
|
|
|
|
// AXI4-lite master memory interface
|
|
|
|
output mem_axi_awvalid,
|
|
input mem_axi_awready,
|
|
output [31:0] mem_axi_awaddr,
|
|
output [ 2:0] mem_axi_awprot,
|
|
|
|
output mem_axi_wvalid,
|
|
input mem_axi_wready,
|
|
output [31:0] mem_axi_wdata,
|
|
output [ 3:0] mem_axi_wstrb,
|
|
|
|
input mem_axi_bvalid,
|
|
output mem_axi_bready,
|
|
|
|
output mem_axi_arvalid,
|
|
input mem_axi_arready,
|
|
output [31:0] mem_axi_araddr,
|
|
output [ 2:0] mem_axi_arprot,
|
|
|
|
input mem_axi_rvalid,
|
|
output mem_axi_rready,
|
|
input [31:0] mem_axi_rdata,
|
|
|
|
// Pico Co-Processor Interface (PCPI)
|
|
output pcpi_valid,
|
|
output [31:0] pcpi_insn,
|
|
output [31:0] pcpi_rs1,
|
|
output [31:0] pcpi_rs2,
|
|
input pcpi_wr,
|
|
input [31:0] pcpi_rd,
|
|
input pcpi_wait,
|
|
input pcpi_ready,
|
|
|
|
// IRQ interface
|
|
input [31:0] irq,
|
|
output [31:0] eoi
|
|
);
|
|
wire mem_valid;
|
|
wire [31:0] mem_addr;
|
|
wire [31:0] mem_wdata;
|
|
wire [ 3:0] mem_wstrb;
|
|
wire mem_instr;
|
|
wire mem_ready;
|
|
wire [31:0] mem_rdata;
|
|
|
|
picorv32_axi_adapter axi_adapter (
|
|
.clk (clk ),
|
|
.resetn (resetn ),
|
|
.mem_axi_awvalid(mem_axi_awvalid),
|
|
.mem_axi_awready(mem_axi_awready),
|
|
.mem_axi_awaddr (mem_axi_awaddr ),
|
|
.mem_axi_awprot (mem_axi_awprot ),
|
|
.mem_axi_wvalid (mem_axi_wvalid ),
|
|
.mem_axi_wready (mem_axi_wready ),
|
|
.mem_axi_wdata (mem_axi_wdata ),
|
|
.mem_axi_wstrb (mem_axi_wstrb ),
|
|
.mem_axi_bvalid (mem_axi_bvalid ),
|
|
.mem_axi_bready (mem_axi_bready ),
|
|
.mem_axi_arvalid(mem_axi_arvalid),
|
|
.mem_axi_arready(mem_axi_arready),
|
|
.mem_axi_araddr (mem_axi_araddr ),
|
|
.mem_axi_arprot (mem_axi_arprot ),
|
|
.mem_axi_rvalid (mem_axi_rvalid ),
|
|
.mem_axi_rready (mem_axi_rready ),
|
|
.mem_axi_rdata (mem_axi_rdata ),
|
|
.mem_valid (mem_valid ),
|
|
.mem_instr (mem_instr ),
|
|
.mem_ready (mem_ready ),
|
|
.mem_addr (mem_addr ),
|
|
.mem_wdata (mem_wdata ),
|
|
.mem_wstrb (mem_wstrb ),
|
|
.mem_rdata (mem_rdata )
|
|
);
|
|
|
|
picorv32 #(
|
|
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
|
|
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
|
|
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
|
|
.CATCH_MISALIGN (CATCH_MISALIGN ),
|
|
.CATCH_ILLINSN (CATCH_ILLINSN ),
|
|
.ENABLE_PCPI (ENABLE_PCPI ),
|
|
.ENABLE_MUL (ENABLE_MUL ),
|
|
.ENABLE_IRQ (ENABLE_IRQ ),
|
|
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
|
|
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
|
|
.MASKED_IRQ (MASKED_IRQ ),
|
|
.LATCHED_IRQ (LATCHED_IRQ ),
|
|
.PROGADDR_RESET (PROGADDR_RESET ),
|
|
.PROGADDR_IRQ (PROGADDR_IRQ )
|
|
) picorv32_core (
|
|
.clk (clk ),
|
|
.resetn (resetn),
|
|
.trap (trap ),
|
|
|
|
.mem_valid(mem_valid),
|
|
.mem_addr (mem_addr ),
|
|
.mem_wdata(mem_wdata),
|
|
.mem_wstrb(mem_wstrb),
|
|
.mem_instr(mem_instr),
|
|
.mem_ready(mem_ready),
|
|
.mem_rdata(mem_rdata),
|
|
|
|
.pcpi_valid(pcpi_valid),
|
|
.pcpi_insn (pcpi_insn ),
|
|
.pcpi_rs1 (pcpi_rs1 ),
|
|
.pcpi_rs2 (pcpi_rs2 ),
|
|
.pcpi_wr (pcpi_wr ),
|
|
.pcpi_rd (pcpi_rd ),
|
|
.pcpi_wait (pcpi_wait ),
|
|
.pcpi_ready(pcpi_ready),
|
|
|
|
.irq(irq),
|
|
.eoi(eoi)
|
|
);
|
|
endmodule
|
|
|
|
|
|
/***************************************************************
|
|
* picorv32_axi_adapter
|
|
***************************************************************/
|
|
|
|
module picorv32_axi_adapter (
|
|
input clk, resetn,
|
|
|
|
// AXI4-lite master memory interface
|
|
|
|
output mem_axi_awvalid,
|
|
input mem_axi_awready,
|
|
output [31:0] mem_axi_awaddr,
|
|
output [ 2:0] mem_axi_awprot,
|
|
|
|
output mem_axi_wvalid,
|
|
input mem_axi_wready,
|
|
output [31:0] mem_axi_wdata,
|
|
output [ 3:0] mem_axi_wstrb,
|
|
|
|
input mem_axi_bvalid,
|
|
output mem_axi_bready,
|
|
|
|
output mem_axi_arvalid,
|
|
input mem_axi_arready,
|
|
output [31:0] mem_axi_araddr,
|
|
output [ 2:0] mem_axi_arprot,
|
|
|
|
input mem_axi_rvalid,
|
|
output mem_axi_rready,
|
|
input [31:0] mem_axi_rdata,
|
|
|
|
// Native PicoRV32 memory interface
|
|
|
|
input mem_valid,
|
|
input mem_instr,
|
|
output mem_ready,
|
|
input [31:0] mem_addr,
|
|
input [31:0] mem_wdata,
|
|
input [ 3:0] mem_wstrb,
|
|
output [31:0] mem_rdata
|
|
);
|
|
reg ack_awvalid;
|
|
reg ack_arvalid;
|
|
reg ack_wvalid;
|
|
|
|
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
|
|
assign mem_axi_awaddr = mem_addr;
|
|
assign mem_axi_awprot = 0;
|
|
|
|
assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
|
|
assign mem_axi_araddr = mem_addr;
|
|
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
|
|
|
|
assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
|
|
assign mem_axi_wdata = mem_wdata;
|
|
assign mem_axi_wstrb = mem_wstrb;
|
|
|
|
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
|
|
assign mem_axi_bready = mem_valid && |mem_wstrb;
|
|
assign mem_axi_rready = mem_valid && !mem_wstrb;
|
|
assign mem_rdata = mem_axi_rdata;
|
|
|
|
always @(posedge clk) begin
|
|
if (!resetn) begin
|
|
ack_awvalid <= 0;
|
|
end else begin
|
|
if (mem_axi_awready && mem_axi_awvalid)
|
|
ack_awvalid <= 1;
|
|
if (mem_axi_arready && mem_axi_arvalid)
|
|
ack_arvalid <= 1;
|
|
if (mem_axi_wready && mem_axi_wvalid)
|
|
ack_wvalid <= 1;
|
|
if (!mem_valid) begin
|
|
ack_awvalid <= 0;
|
|
ack_arvalid <= 0;
|
|
ack_wvalid <= 0;
|
|
end
|
|
end
|
|
end
|
|
endmodule
|
|
|