mirror of https://github.com/YosysHQ/picorv32.git
85 lines
2.1 KiB
Verilog
85 lines
2.1 KiB
Verilog
module testbench (
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`ifdef VERILATOR
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input clk
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`endif
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);
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`ifndef VERILATOR
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reg clk = 1;
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always #5 clk = ~clk;
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`endif
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reg resetn = 0;
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wire trap;
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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picorv32 #(
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.COMPRESSED_ISA(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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reg [1023:0] hex_filename;
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reg [1023:0] ref_filename;
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reg [31:0] memory [0:4095];
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reg [31:0] memory_ref [0:4095];
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integer i, errcount;
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initial begin
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if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory);
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if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref);
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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repeat (10) @(posedge clk);
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resetn <= 1;
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end
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always @(posedge clk) begin
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mem_ready <= 0;
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mem_rdata <= 'bx;
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if (!trap || !resetn) begin
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if (mem_valid && !mem_ready && resetn) begin
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mem_ready <= 1;
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if (mem_wstrb) begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end else begin
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mem_rdata <= memory[mem_addr >> 2];
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end
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end
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end else begin
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errcount = 0;
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for (i=0; i < 4096; i=i+1) begin
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if (memory[i] !== memory_ref[i]) begin
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$display("Signature check failed at %04x: mem=%08x ref=%08x", i << 2, memory[i], memory_ref[i]);
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errcount = errcount + 1;
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end
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end
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if (errcount)
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$display("FAILED: Got %1d errors for %1s/%1s!", errcount, hex_filename, ref_filename);
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else
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$display("PASSED %1s/%1s.", hex_filename, ref_filename);
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$finish;
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end
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end
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endmodule
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