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8 lines
172 B
Tcl
8 lines
172 B
Tcl
read_verilog ../../picorv32.v
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read_xdc synth_area.xdc
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synth_design -part xc7k70t-fbg676 -top picorv32_axi
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opt_design -resynth_seq_area
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report_utilization
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# report_timing
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