mirror of https://github.com/YosysHQ/picorv32.git
95 lines
2.1 KiB
Verilog
95 lines
2.1 KiB
Verilog
`timescale 1 ns / 1 ps
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module top (
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input clk_pin,
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output reg LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7
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);
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// -------------------------------
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// Clock Buffer
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wire clk;
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`ifdef USE_SB_GB_IO
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SB_GB_IO #(
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.PIN_TYPE(6'b 0000_01)
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) clk_gb (
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.PACKAGE_PIN(clk_pin),
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.GLOBAL_BUFFER_OUTPUT(clk)
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);
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`else
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assign clk = clk_pin;
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`endif
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// -------------------------------
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// Reset Generator
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reg [7:0] resetn_counter = 0;
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wire resetn = &resetn_counter;
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always @(posedge clk) begin
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if (!resetn)
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resetn_counter <= resetn_counter + 1;
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end
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// -------------------------------
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// PicoRV32 Core
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wire mem_valid;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg mem_ready;
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reg [31:0] mem_rdata;
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.LATCHED_MEM_RDATA(1),
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.TWO_STAGE_SHIFT(0),
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.TWO_CYCLE_ALU(1),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0)
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.mem_valid(mem_valid),
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.mem_ready(mem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata)
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);
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// -------------------------------
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// Memory/IO Interface
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// 128 32bit words = 512 bytes memory
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localparam MEM_SIZE = 128;
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reg [31:0] memory [0:MEM_SIZE-1];
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initial $readmemh("firmware.hex", memory);
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always @(posedge clk) begin
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mem_ready <= 0;
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if (resetn && mem_valid && !mem_ready) begin
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(* parallel_case *)
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case (1)
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!mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
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mem_rdata <= memory[mem_addr >> 2];
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mem_ready <= 1;
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end
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|mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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mem_ready <= 1;
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end
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|mem_wstrb && mem_addr == 32'h1000_0000: begin
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{LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
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mem_ready <= 1;
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end
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endcase
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end
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end
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endmodule
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