mirror of https://github.com/YosysHQ/picorv32.git
110 lines
2.6 KiB
Verilog
110 lines
2.6 KiB
Verilog
/*
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* Interface module for SPI flash and PicoRV32 native memory interface
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module spimemio (
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input clk, resetn,
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input valid,
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output reg ready,
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input [23:0] addr,
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output reg [31:0] rdata,
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output reg flash_csb,
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output reg flash_clk,
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output flash_io0,
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input flash_io1,
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input flash_io2,
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input flash_io3
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);
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parameter ENABLE_PREFETCH = 1;
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reg [23:0] addr_q;
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reg addr_q_vld;
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reg [31:0] buffer;
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reg [6:0] xfer_cnt;
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reg xfer_wait;
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reg prefetch;
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reg spi_mosi;
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wire spi_miso;
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assign flash_io0 = spi_mosi;
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assign spi_miso = flash_io1;
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always @(posedge clk) begin
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ready <= 0;
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if (!resetn) begin
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flash_csb <= 1;
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flash_clk <= 1;
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xfer_cnt <= 8;
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buffer <= 8'hAB << 24;
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addr_q_vld <= 0;
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xfer_wait <= 0;
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prefetch <= 0;
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end else
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if (xfer_cnt) begin
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if (flash_csb) begin
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flash_csb <= 0;
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end else
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if (flash_clk) begin
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flash_clk <= 0;
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spi_mosi <= buffer[31];
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end else begin
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flash_clk <= 1;
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buffer <= {buffer, spi_miso};
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xfer_cnt <= xfer_cnt - 1;
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end
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end else
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if (xfer_wait) begin
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ready <= 1;
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rdata <= {buffer[7:0], buffer[15:8], buffer[23:16], buffer[31:24]};
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xfer_wait <= 0;
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end else
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if (valid && !ready) begin
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if (addr_q_vld && addr_q == addr) begin
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addr_q <= addr + 4;
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addr_q_vld <= 1;
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if (!prefetch)
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xfer_cnt <= 32;
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xfer_wait <= 1;
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prefetch <= 0;
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end else begin
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flash_csb <= 1;
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buffer <= {8'h 03, addr};
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addr_q <= addr + 4;
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addr_q_vld <= 1;
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xfer_cnt <= 64;
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xfer_wait <= 1;
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prefetch <= 0;
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end
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end else if (ENABLE_PREFETCH && !prefetch) begin
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prefetch <= 1;
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xfer_cnt <= 32;
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end
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if (ENABLE_PREFETCH && resetn && prefetch && valid && !ready && addr_q != addr) begin
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prefetch <= 0;
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xfer_cnt <= 0;
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xfer_wait <= 0;
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flash_clk <= 1;
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end
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end
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endmodule
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