mirror of https://github.com/YosysHQ/picorv32.git
112 lines
3.1 KiB
Verilog
112 lines
3.1 KiB
Verilog
/*
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* Top-level for "spiflash" SoC demo
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module top (
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input clk,
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output trap,
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input [31:0] gpio_i,
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output reg [31:0] gpio_o,
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output flash_csb,
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output flash_clk,
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output flash_io0,
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input flash_io1,
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input flash_io2,
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input flash_io3
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);
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parameter integer MEM_WORDS = 256;
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parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
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parameter [31:0] PROGADDR_RESET = 32'h 8010_0000; // 1 MB into flash
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reg [5:0] reset_cnt = 0;
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wire resetn = &reset_cnt;
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always @(posedge clk) begin
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reset_cnt <= reset_cnt + !resetn;
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end
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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wire spimem_ready;
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wire [31:0] spimem_rdata;
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picorv32 #(
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.STACKADDR(STACKADDR),
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.PROGADDR_RESET(PROGADDR_RESET)
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready || spimem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (spimem_ready ? spimem_rdata : mem_rdata )
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);
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spimemio spimemio (
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.clk(clk),
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.resetn(resetn),
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.valid (mem_valid && mem_addr[31:30] == 2'b10),
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.ready (spimem_ready),
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.addr (mem_addr[23:0]),
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.rdata (spimem_rdata),
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.flash_csb (flash_csb),
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.flash_clk (flash_clk),
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.flash_io0 (flash_io0),
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.flash_io1 (flash_io1),
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.flash_io2 (flash_io2),
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.flash_io3 (flash_io3)
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);
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reg [31:0] memory [0:MEM_WORDS-1];
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always @(posedge clk) begin
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mem_ready <= 0;
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if (mem_valid && !mem_ready) begin
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if (mem_addr < 4*MEM_WORDS) begin
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mem_ready <= 1;
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mem_rdata <= memory[mem_addr >> 2];
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end
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if (mem_addr == 32'h c000_0000) begin
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mem_ready <= 1;
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mem_rdata <= gpio_i;
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if (mem_wstrb[0]) gpio_o[ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) gpio_o[15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) gpio_o[23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) gpio_o[31:24] <= mem_wdata[31:24];
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end
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end
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end
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endmodule
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