mirror of https://github.com/YosysHQ/picorv32.git
45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
module main (input clk, resetn, domem, output trap);
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parameter [0:0] ENABLE_REGS_DUALPORT = 1;
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parameter [0:0] TWO_STAGE_SHIFT = 1;
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parameter [0:0] TWO_CYCLE_COMPARE = 0;
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parameter [0:0] TWO_CYCLE_ALU = 0;
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(* keep *) wire mem_valid;
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(* keep *) wire mem_ready;
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(* keep *) wire [31:0] mem_addr;
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(* keep *) wire [31:0] mem_wdata;
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(* keep *) wire [ 3:0] mem_wstrb;
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(* keep *) wire [31:0] mem_rdata;
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picorv32 #(
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
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.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
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.TWO_CYCLE_ALU (TWO_CYCLE_ALU )
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid(mem_valid),
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.mem_ready(mem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata)
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);
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reg [31:0] memory [0:2**30-1];
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assign mem_ready = domem && resetn && mem_valid;
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assign mem_rdata = memory[mem_addr >> 2];
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always @(posedge clk) begin
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if (mem_ready && mem_valid) begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end
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end
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endmodule
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