mirror of https://github.com/YosysHQ/picorv32.git
160 lines
2.4 KiB
ArmAsm
160 lines
2.4 KiB
ArmAsm
.section .text
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start:
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# zero-initialize register file
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addi x1, zero, 0
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# x2 (sp) is initialized by reset
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addi x3, zero, 0
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addi x4, zero, 0
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addi x5, zero, 0
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addi x6, zero, 0
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addi x7, zero, 0
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addi x8, zero, 0
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addi x9, zero, 0
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addi x10, zero, 0
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addi x11, zero, 0
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addi x12, zero, 0
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addi x13, zero, 0
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addi x14, zero, 0
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addi x15, zero, 0
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addi x16, zero, 0
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addi x17, zero, 0
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addi x18, zero, 0
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addi x19, zero, 0
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addi x20, zero, 0
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addi x21, zero, 0
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addi x22, zero, 0
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addi x23, zero, 0
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addi x24, zero, 0
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addi x25, zero, 0
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addi x26, zero, 0
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addi x27, zero, 0
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addi x28, zero, 0
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addi x29, zero, 0
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addi x30, zero, 0
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addi x31, zero, 0
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# Update LEDs
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li a0, 0x03000000
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li a1, 1
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sw a1, 0(a0)
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# zero initialize entire scratchpad memory
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li a0, 0x00000000
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setmemloop:
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sw a0, 0(a0)
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addi a0, a0, 4
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blt a0, sp, setmemloop
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# Update LEDs
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li a0, 0x03000000
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li a1, 3
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sw a1, 0(a0)
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# copy data section
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la a0, _sidata
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la a1, _sdata
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la a2, _edata
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bge a1, a2, end_init_data
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loop_init_data:
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lw a3, 0(a0)
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sw a3, 0(a1)
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addi a0, a0, 4
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addi a1, a1, 4
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blt a1, a2, loop_init_data
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end_init_data:
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# Update LEDs
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li a0, 0x03000000
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li a1, 7
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sw a1, 0(a0)
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# zero-init bss section
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la a0, _sbss
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la a1, _ebss
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bge a0, a1, end_init_bss
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loop_init_bss:
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sw zero, 0(a0)
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addi a0, a0, 4
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blt a0, a1, loop_init_bss
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end_init_bss:
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# Update LEDs
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li a0, 0x03000000
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li a1, 15
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sw a1, 0(a0)
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# call main
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call main
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loop:
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j loop
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.global flashio_worker_begin
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.global flashio_worker_end
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.balign 4
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flashio_worker_begin:
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# a0 ... data pointer
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# a1 ... data length
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# a2 ... optional WREN cmd (0 = disable)
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# address of SPI ctrl reg
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li t0, 0x02000000
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# Set CS high, IO0 is output
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li t1, 0x120
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sh t1, 0(t0)
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# Enable Manual SPI Ctrl
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sb zero, 3(t0)
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# Send optional WREN cmd
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beqz a2, flashio_worker_L1
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li t5, 8
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andi t2, a2, 0xff
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flashio_worker_L4:
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srli t4, t2, 7
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sb t4, 0(t0)
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ori t4, t4, 0x10
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sb t4, 0(t0)
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slli t2, t2, 1
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andi t2, t2, 0xff
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addi t5, t5, -1
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bnez t5, flashio_worker_L4
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sb t1, 0(t0)
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# SPI transfer
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flashio_worker_L1:
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beqz a1, flashio_worker_L3
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li t5, 8
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lbu t2, 0(a0)
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flashio_worker_L2:
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srli t4, t2, 7
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sb t4, 0(t0)
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ori t4, t4, 0x10
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sb t4, 0(t0)
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lbu t4, 0(t0)
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andi t4, t4, 2
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srli t4, t4, 1
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slli t2, t2, 1
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or t2, t2, t4
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andi t2, t2, 0xff
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addi t5, t5, -1
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bnez t5, flashio_worker_L2
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sb t2, 0(a0)
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addi a0, a0, 1
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addi a1, a1, -1
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j flashio_worker_L1
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flashio_worker_L3:
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# Back to MEMIO mode
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li t1, 0x80
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sb t1, 3(t0)
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ret
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.balign 4
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flashio_worker_end:
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