mirror of https://github.com/YosysHQ/picorv32.git
32 lines
661 B
Plaintext
32 lines
661 B
Plaintext
read_verilog main.v
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read_verilog ../../picorv32.v
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rename main main_a
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chparam -set ENABLE_REGS_DUALPORT 0 \
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-set TWO_STAGE_SHIFT 0 \
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-set TWO_CYCLE_COMPARE 0 \
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-set TWO_CYCLE_ALU 0 main_a
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hierarchy -top main_a
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proc
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opt
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memory -nordff -nomap
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flatten
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opt
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write_smt2 -bv -mem -regs async_a.smt2
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design -reset
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read_verilog main.v
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read_verilog ../../picorv32.v
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rename main main_b
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chparam -set ENABLE_REGS_DUALPORT 1 \
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-set TWO_STAGE_SHIFT 1 \
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-set TWO_CYCLE_COMPARE 1 \
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-set TWO_CYCLE_ALU 1 main_b
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hierarchy -top main_b
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proc
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opt
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memory -nordff -nomap
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flatten
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opt
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write_smt2 -bv -mem -regs async_b.smt2
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design -reset
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