mirror of https://github.com/YosysHQ/picorv32.git
83 lines
1.6 KiB
Verilog
83 lines
1.6 KiB
Verilog
module spimemio (
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input clk, resetn,
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input valid,
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output reg ready,
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input [23:0] addr,
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output reg [31:0] rdata,
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output reg spi_cs,
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output reg spi_sclk,
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output reg spi_mosi,
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input spi_miso
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);
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parameter ENABLE_PREFETCH = 1;
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reg [23:0] addr_q;
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reg addr_q_vld;
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reg [31:0] buffer;
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reg [6:0] xfer_cnt;
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reg xfer_wait;
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reg prefetch;
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always @(posedge clk) begin
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ready <= 0;
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if (!resetn) begin
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spi_cs <= 1;
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spi_sclk <= 1;
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xfer_cnt <= 8;
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buffer <= 8'hAB << 24;
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addr_q_vld <= 0;
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xfer_wait <= 0;
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prefetch <= 0;
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end else
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if (xfer_cnt) begin
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if (spi_cs) begin
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spi_cs <= 0;
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end else
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if (spi_sclk) begin
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spi_sclk <= 0;
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spi_mosi <= buffer[31];
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end else begin
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spi_sclk <= 1;
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buffer <= {buffer, spi_miso};
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xfer_cnt <= xfer_cnt - 1;
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end
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end else
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if (xfer_wait) begin
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ready <= 1;
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rdata <= {buffer[7:0], buffer[15:8], buffer[23:16], buffer[31:24]};
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xfer_wait <= 0;
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end else
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if (valid && !ready) begin
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if (addr_q_vld && addr_q == addr) begin
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addr_q <= addr + 4;
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addr_q_vld <= 1;
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if (!prefetch)
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xfer_cnt <= 32;
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xfer_wait <= 1;
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prefetch <= 0;
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end else begin
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spi_cs <= 1;
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buffer <= {8'h 03, addr};
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addr_q <= addr + 4;
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addr_q_vld <= 1;
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xfer_cnt <= 64;
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xfer_wait <= 1;
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prefetch <= 0;
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end
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end else if (ENABLE_PREFETCH && !prefetch) begin
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prefetch <= 1;
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xfer_cnt <= 32;
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end
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if (ENABLE_PREFETCH && resetn && prefetch && valid && !ready && addr_q != addr) begin
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prefetch <= 0;
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xfer_cnt <= 0;
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xfer_wait <= 0;
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spi_sclk <= 1;
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end
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end
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endmodule
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