mirror of https://github.com/YosysHQ/picorv32.git
50 lines
815 B
Verilog
50 lines
815 B
Verilog
module testbench;
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reg clk = 1;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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repeat (100000) @(posedge clk);
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$display("");
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$display("[TIMEOUT]");
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$stop;
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end
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wire [31:0] gpio_i = 0;
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wire [31:0] gpio_o;
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wire spi_cs;
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wire spi_sclk;
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wire spi_mosi;
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wire spi_miso;
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always @(gpio_o) begin
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$write("<GPIO:%02x>", gpio_o[7:0]);
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if (gpio_o == 63) begin
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$display("[OK]");
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$finish;
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end
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if (gpio_o % 8 == 7) begin
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$display("");
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end
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end
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top uut (
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.clk (clk ),
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.gpio_i (gpio_i ),
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.gpio_o (gpio_o ),
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.spi_cs (spi_cs ),
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.spi_sclk(spi_sclk),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso)
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);
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spiflash spiflash (
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.spi_cs (spi_cs ),
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.spi_sclk(spi_sclk),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso)
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);
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endmodule
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