mirror of https://github.com/YosysHQ/picorv32.git
44 lines
855 B
Verilog
44 lines
855 B
Verilog
// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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`timescale 1 ns / 1 ps
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// `define VERBOSE
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module testbench #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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);
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reg clk = 1;
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reg resetn = 0;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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repeat (1000000) @(posedge clk);
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$display("TIMEOUT");
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$finish;
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end
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picorv32_wrapper #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) top (
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.clk (clk ),
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.resetn (resetn)
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);
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endmodule
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