mirror of https://github.com/YosysHQ/picorv32.git
290 lines
4.3 KiB
ArmAsm
290 lines
4.3 KiB
ArmAsm
#define ENABLE_RVTST
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#define ENABLE_SIEVE
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#define ENABLE_MULTST
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#define ENABLE_STATS
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.section .text
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.global irq
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.global sieve
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.global multest
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.global hard_mul
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.global hard_mulh
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.global hard_mulhsu
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.global hard_mulhu
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.global stats
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#ifdef ENABLE_RVTST
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# define TEST(n) \
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.global n; \
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addi x1, zero, 1000; \
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custom0 0,1,0,5; /* timer zero, x1 */ \
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jal zero,n; \
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.global n ## _ret; \
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n ## _ret:
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#else
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# define TEST(n) \
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.global n ## _ret; \
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n ## _ret:
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#endif
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reset_vec:
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custom0 0,0,0,4 // waitirq zero
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custom0 0,0,0,3 // maskirq zero, zero
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j start
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nop
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nop
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irq_vec:
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/* save registers */
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custom0 2,1,0,1 // setq q2, x1
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custom0 3,2,0,1 // setq q3, x2
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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custom0 2,0,0,0 // getq x2, q0
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sw x2, 0*4(x1)
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custom0 2,2,0,0 // getq x2, q2
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sw x2, 1*4(x1)
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custom0 2,3,0,0 // getq x2, q3
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sw x2, 2*4(x1)
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sw x3, 3*4(x1)
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sw x4, 4*4(x1)
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x8, 8*4(x1)
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sw x9, 9*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x18, 18*4(x1)
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sw x19, 19*4(x1)
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sw x20, 20*4(x1)
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sw x21, 21*4(x1)
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sw x22, 22*4(x1)
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sw x23, 23*4(x1)
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sw x24, 24*4(x1)
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sw x25, 25*4(x1)
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sw x26, 26*4(x1)
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sw x27, 27*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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/* call interrupt handler */
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lui sp, %hi(irq_stack_top)
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addi sp, sp, %lo(irq_stack_top)
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// arg0 = address of regs
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lui a0, %hi(irq_regs)
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addi a0, a0, %lo(irq_regs)
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// arg1 = interrupt type
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custom0 11,1,0,0 // getq x11, q1
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// call to c function
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jal ra, irq
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/* restore registers */
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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lw x2, 0*4(x1)
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custom0 0,2,0,1 // setq q0, x2
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lw x2, 1*4(x1)
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custom0 1,2,0,1 // setq q1, x2
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lw x2, 2*4(x1)
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custom0 2,2,0,1 // setq q2, x2
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lw x3, 3*4(x1)
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lw x4, 4*4(x1)
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x8, 8*4(x1)
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lw x9, 9*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x18, 18*4(x1)
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lw x19, 19*4(x1)
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lw x20, 20*4(x1)
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lw x21, 21*4(x1)
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lw x22, 22*4(x1)
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lw x23, 23*4(x1)
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lw x24, 24*4(x1)
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lw x25, 25*4(x1)
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lw x26, 26*4(x1)
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lw x27, 27*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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custom0 1,1,0,0 // getq x1, q1
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custom0 2,2,0,0 // getq x2, q2
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custom0 0,0,0,2 // retirq
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irq_regs:
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// registers are saved to this memory region
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// the program counter is saved as register 0
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.fill 32,4
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irq_stack:
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.fill 128,4
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irq_stack_top:
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start:
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addi x1, zero, 0
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addi x2, zero, 0
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addi x3, zero, 0
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addi x4, zero, 0
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addi x5, zero, 0
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addi x6, zero, 0
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addi x7, zero, 0
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addi x8, zero, 0
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addi x9, zero, 0
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addi x10, zero, 0
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addi x11, zero, 0
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addi x12, zero, 0
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addi x13, zero, 0
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addi x14, zero, 0
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addi x15, zero, 0
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addi x16, zero, 0
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addi x17, zero, 0
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addi x18, zero, 0
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addi x19, zero, 0
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addi x20, zero, 0
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addi x21, zero, 0
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addi x22, zero, 0
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addi x23, zero, 0
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addi x24, zero, 0
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addi x25, zero, 0
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addi x26, zero, 0
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addi x27, zero, 0
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addi x28, zero, 0
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addi x29, zero, 0
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addi x30, zero, 0
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addi x31, zero, 0
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TEST(lui)
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TEST(auipc)
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TEST(j)
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TEST(jal)
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TEST(jalr)
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TEST(beq)
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TEST(bne)
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TEST(blt)
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TEST(bge)
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TEST(bltu)
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TEST(bgeu)
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TEST(lb)
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TEST(lh)
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TEST(lw)
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TEST(lbu)
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TEST(lhu)
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TEST(sb)
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TEST(sh)
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TEST(sw)
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TEST(addi)
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TEST(slti) // also tests sltiu
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TEST(xori)
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TEST(ori)
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TEST(andi)
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TEST(slli)
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TEST(srli)
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TEST(srai)
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TEST(add)
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TEST(sub)
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TEST(sll)
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TEST(slt) // what is with sltu ?
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TEST(xor)
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TEST(srl)
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TEST(sra)
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TEST(or)
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TEST(and)
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TEST(mulh)
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TEST(mulhsu)
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TEST(mulhu)
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TEST(mul)
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TEST(simple)
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/* set stack pointer */
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lui sp,(64*1024)>>12
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#ifdef ENABLE_SIEVE
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/* call sieve C code */
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jal ra,sieve
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#endif
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#ifdef ENABLE_MULTST
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/* call sieve C code */
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jal ra,multest
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#endif
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#ifdef ENABLE_STATS
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/* call stats C code */
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jal ra,stats
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#endif
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/* print "DONE\n" */
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lui a0,0x10000000>>12
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addi a1,zero,'D'
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addi a2,zero,'O'
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addi a3,zero,'N'
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addi a4,zero,'E'
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addi a5,zero,'\n'
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sw a1,0(a0)
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sw a2,0(a0)
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sw a3,0(a0)
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sw a4,0(a0)
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sw a5,0(a0)
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/* break */
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sbreak
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hard_mul:
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mul a0, a0, a1
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ret
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hard_mulh:
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mulh a0, a0, a1
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ret
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hard_mulhsu:
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mulhsu a0, a0, a1
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ret
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hard_mulhu:
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mulhu a0, a0, a1
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ret
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