mirror of https://github.com/YosysHQ/picorv32.git
109 lines
2.4 KiB
Verilog
109 lines
2.4 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk;
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always #5 clk = (clk === 1'b0);
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localparam ser_half_period = 53;
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event ser_sample;
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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repeat (6) begin
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repeat (50000) @(posedge clk);
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$display("+50000 cycles");
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end
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$finish;
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end
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integer cycle_cnt = 0;
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always @(posedge clk) begin
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cycle_cnt <= cycle_cnt + 1;
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end
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wire [7:0] leds;
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wire ser_rx;
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wire ser_tx;
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wire flash_csb;
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wire flash_clk;
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wire flash_io0;
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wire flash_io1;
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wire flash_io2;
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wire flash_io3;
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always @(leds) begin
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#1 $display("%b", leds);
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end
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hx8kdemo uut (
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.clk (clk ),
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.leds (leds ),
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.ser_rx (ser_rx ),
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.ser_tx (ser_tx ),
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.flash_csb(flash_csb),
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.flash_clk(flash_clk),
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.flash_io0(flash_io0),
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.flash_io1(flash_io1),
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.flash_io2(flash_io2),
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.flash_io3(flash_io3)
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);
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spiflash spiflash (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(flash_io2),
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.io3(flash_io3)
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);
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reg [7:0] buffer;
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always begin
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@(negedge ser_tx);
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repeat (ser_half_period) @(posedge clk);
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-> ser_sample; // start bit
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repeat (8) begin
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repeat (ser_half_period) @(posedge clk);
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repeat (ser_half_period) @(posedge clk);
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buffer = {ser_tx, buffer[7:1]};
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-> ser_sample; // data bit
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end
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repeat (ser_half_period) @(posedge clk);
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repeat (ser_half_period) @(posedge clk);
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-> ser_sample; // stop bit
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if (buffer < 32 || buffer >= 127)
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$display("Serial data: %d", buffer);
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else
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$display("Serial data: '%c'", buffer);
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end
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endmodule
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