mirror of https://github.com/YosysHQ/picorv32.git
324 lines
15 KiB
Python
324 lines
15 KiB
Python
#!/usr/bin/python3
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import os, sys, getopt
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from time import time
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from smtio import smtio
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steps = 12
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words = 0
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solver = "yices"
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allmem = False
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fastmem = False
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initzero = False
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check_mem = True
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check_regs = True
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debug_print = False
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debug_file = open("debug.smt2", "w")
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start_time = time()
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smt = smtio(solver=solver, debug_print=debug_print, debug_file=debug_file)
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def timestamp():
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secs = int(time() - start_time)
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return "+ %6d [%3d:%02d:%02d] " % (secs, secs // (60*60), (secs // 60) % 60, secs % 60)
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smt.write("(set-logic QF_AUFBV)")
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regs_a = list()
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regs_b = list()
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with open("async_a.smt2", "r") as f:
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for line in f:
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if line.startswith("; yosys-smt2-register "):
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line = line.split()
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regs_a.append((line[2], int(line[3])))
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else:
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smt.write(line)
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with open("async_b.smt2", "r") as f:
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for line in f:
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if line.startswith("; yosys-smt2-register "):
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line = line.split()
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regs_b.append((line[2], int(line[3])))
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else:
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smt.write(line)
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for step in range(steps):
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smt.write("(declare-fun a%d () main_a_s)" % step)
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smt.write("(declare-fun b%d () main_b_s)" % step)
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if fastmem:
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smt.write("(assert (|main_a_n domem| a%d))" % step)
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smt.write("(assert (|main_b_n domem| b%d))" % step)
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if words > 0:
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if allmem:
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smt.write("(assert (bvult (|main_a_n mem_addr| a%d) #x%08x))" % (step, words))
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smt.write("(assert (bvult (|main_b_n mem_addr| b%d) #x%08x))" % (step, words))
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else:
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smt.write("(assert (or (not (|main_a_n mem_valid| a%d)) (bvult (|main_a_n mem_addr| a%d) #x%08x)))" % (step, step, words))
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smt.write("(assert (or (not (|main_b_n mem_valid| b%d)) (bvult (|main_b_n mem_addr| b%d) #x%08x)))" % (step, step, words))
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if step == 0:
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# start with synced memory and register file
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smt.write("(assert (= (|main_a_m cpu.cpuregs| a0) (|main_b_m cpu.cpuregs| b0)))")
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smt.write("(assert (= (|main_a_m memory| a0) (|main_b_m memory| b0)))")
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# reset in first cycle
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smt.write("(assert (not (|main_a_n resetn| a%d)))" % step)
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smt.write("(assert (not (|main_b_n resetn| b%d)))" % step)
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else:
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smt.write("(assert (main_a_t a%d a%d))" % (step-1, step))
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smt.write("(assert (main_b_t b%d b%d))" % (step-1, step))
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smt.write("(assert (|main_a_n resetn| a%d))" % step)
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smt.write("(assert (|main_b_n resetn| b%d))" % step)
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print("%s Checking sequence of length %d.." % (timestamp(), step))
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smt.write("(push 1)")
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# stop with a trap and no pending memory xfer
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smt.write("(assert (not (|main_a_n mem_valid| a%d)))" % step)
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smt.write("(assert (not (|main_b_n mem_valid| b%d)))" % step)
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smt.write("(assert (|main_a_n trap| a%d))" % step)
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smt.write("(assert (|main_b_n trap| b%d))" % step)
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# look for differences in memory and/or register file
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if check_mem and check_regs:
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smt.write(("(assert (or (distinct (|main_a_m cpu.cpuregs| a%d) (|main_b_m cpu.cpuregs| b%d)) " +
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"(distinct (|main_a_m memory| a%d) (|main_b_m memory| b%d))))") % (step, step, step, step))
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elif check_mem:
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smt.write(("(assert (distinct (|main_a_m memory| a%d) (|main_b_m memory| b%d)))") % (step, step))
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elif check_regs:
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smt.write(("(assert (distinct (|main_a_m cpu.cpuregs| a%d) (|main_b_m cpu.cpuregs| b%d)))") % (step, step))
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else:
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assert False
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smt.write("(check-sat)")
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if smt.read() == "sat":
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print("%s Creating model.." % timestamp())
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def make_cpu_regs(step):
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for i in range(1, 32):
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smt.write("(define-fun a%d_r%d () (_ BitVec 32) (select (|main_a_m cpu.cpuregs| a%d) #b%s))" % (step, i, step, bin(32+i)[3:]))
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smt.write("(define-fun b%d_r%d () (_ BitVec 32) (select (|main_b_m cpu.cpuregs| b%d) #b%s))" % (step, i, step, bin(32+i)[3:]))
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make_cpu_regs(0)
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make_cpu_regs(step)
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smt.write("(check-sat)")
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def print_status(mod, step):
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resetn = smt.get_net_bool("main_" + mod, "resetn", "%s%d" % (mod, step))
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memvld = smt.get_net_bool("main_" + mod, "mem_valid", "%s%d" % (mod, step))
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domem = smt.get_net_bool("main_" + mod, "domem", "%s%d" % (mod, step))
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memrdy = smt.get_net_bool("main_" + mod, "mem_ready", "%s%d" % (mod, step))
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trap = smt.get_net_bool("main_" + mod, "trap", "%s%d" % (mod, step))
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print("status %5s: resetn=%s, memvld=%s, domem=%s, memrdy=%s, trap=%s" % ("%s[%d]" % (mod, step), resetn, memvld, domem, memrdy, trap))
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def print_mem_xfer(mod, step):
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if allmem or smt.get("(and (|main_%s_n mem_valid| %s%d) (|main_%s_n mem_ready| %s%d))" % (mod, mod, step, mod, mod, step)) == 'true':
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mem_addr = smt.get_net_hex("main_" + mod, "mem_addr", "%s%d" % (mod, step))
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mem_wdata = smt.get_net_hex("main_" + mod, "mem_wdata", "%s%d" % (mod, step))
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mem_wstrb = smt.get_net_bin("main_" + mod, "mem_wstrb", "%s%d" % (mod, step))
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mem_rdata = smt.get_net_hex("main_" + mod, "mem_rdata", "%s%d" % (mod, step))
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if allmem and smt.get("(and (|main_%s_n mem_valid| %s%d) (|main_%s_n mem_ready| %s%d))" % (mod, mod, step, mod, mod, step)) == 'true':
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print("mem %5s: addr=%s, wdata=%s, wstrb=%s, rdata=%s <-" % ("%s[%d]" % (mod, step), mem_addr, mem_wdata, mem_wstrb, mem_rdata))
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else:
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print("mem %5s: addr=%s, wdata=%s, wstrb=%s, rdata=%s" % ("%s[%d]" % (mod, step), mem_addr, mem_wdata, mem_wstrb, mem_rdata))
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def print_cpu_regs(step):
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for i in range(1, 32):
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ra = smt.bv2hex(smt.get("a%d_r%d" % (step, i)))
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rb = smt.bv2hex(smt.get("b%d_r%d" % (step, i)))
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print("%3s[%d]: A=%s B=%s%s" % ("x%d" % i, step, ra, rb, " !" if ra != rb else ""))
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assert smt.read() == "sat"
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if initzero:
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for rn, rs in regs_a:
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force_to_zero = True
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if smt.get_net_bin("main_a", rn, "a0").count("1") != 0:
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print("Looking for a solution with |main_a_n %s| initialized to all zeros.." % rn)
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smt.write("(push 1)")
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if rs == 1:
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smt.write("(assert (not (|main_a_n %s| a0)))" % rn)
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else:
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smt.write("(assert (= (|main_a_n %s| a0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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if smt.read() != "sat":
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force_to_zero = False
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smt.write("(pop 1)")
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if force_to_zero:
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if rs == 1:
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smt.write("(assert (not (|main_a_n %s| a0)))" % rn)
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else:
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smt.write("(assert (= (|main_a_n %s| a0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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assert smt.read() == "sat"
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for rn, rs in regs_b:
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force_to_zero = True
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if smt.get_net_bin("main_b", rn, "b0").count("1") != 0:
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print("Looking for a solution with |main_b_n %s| initialized to all zeros.." % rn)
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smt.write("(push 1)")
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if rs == 1:
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smt.write("(assert (not (|main_b_n %s| b0)))" % rn)
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else:
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smt.write("(assert (= (|main_b_n %s| b0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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if smt.read() != "sat":
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force_to_zero = False
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smt.write("(pop 1)")
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if force_to_zero:
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if rs == 1:
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smt.write("(assert (not (|main_b_n %s| b0)))" % rn)
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else:
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smt.write("(assert (= (|main_b_n %s| b0) #b%s))" % (rn, "0" * rs))
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smt.write("(check-sat)")
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assert smt.read() == "sat"
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print()
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print_cpu_regs(0)
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print()
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print_cpu_regs(step)
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print()
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for i in range(step+1):
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print_status("a", i)
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print()
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for i in range(step+1):
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print_status("b", i)
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print()
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for i in range(1, step+1):
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print_mem_xfer("a", i)
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print()
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for i in range(1, step+1):
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print_mem_xfer("b", i)
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with open("async_tb.v", "w") as f:
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print()
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print("writing verilog test bench...")
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memory_words = 1
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memory_datas = { "a": dict(), "b": dict() }
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for i in range(step, 0, -1):
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for mod in ["a", "b"]:
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if allmem or smt.get("(and (|main_%s_n mem_valid| %s%d) (|main_%s_n mem_ready| %s%d))" % (mod, mod, i, mod, mod, i)) == 'true':
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mem_addr = smt.get_net_hex("main_" + mod, "mem_addr", "%s%d" % (mod, i))
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mem_rdata = smt.get_net_hex("main_" + mod, "mem_rdata", "%s%d" % (mod, i))
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memory_datas[mod][mem_addr] = mem_rdata
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memory_words = max((int(mem_addr, 16) >> 2)+1, memory_words)
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memory_data = dict()
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for k, v in memory_datas["a"].items(): memory_data[k] = v
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for k, v in memory_datas["b"].items(): memory_data[k] = v
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print("`timescale 1 ns / 1 ps", file=f)
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print("", file=f)
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print("module testbench;", file=f)
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print(" reg clk = 1, resetn, domem_a, domem_b;", file=f)
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print(" always #5 clk = ~clk;", file=f)
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print("", file=f)
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print(" main #(", file=f)
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print(" .MEMORY_WORDS(%d)," % memory_words, file=f)
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print(" .ENABLE_REGS_DUALPORT(0),", file=f)
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print(" .TWO_STAGE_SHIFT(0),", file=f)
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print(" .TWO_CYCLE_COMPARE(0),", file=f)
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print(" .TWO_CYCLE_ALU(0)", file=f)
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print(" ) main_a (", file=f)
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print(" .clk(clk),", file=f)
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print(" .resetn(resetn),", file=f)
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print(" .domem(domem_a)", file=f)
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print(" );", file=f)
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print("", file=f)
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print(" main #(", file=f)
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print(" .MEMORY_WORDS(%d)," % memory_words, file=f)
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print(" .ENABLE_REGS_DUALPORT(1),", file=f)
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print(" .TWO_STAGE_SHIFT(1),", file=f)
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print(" .TWO_CYCLE_COMPARE(1),", file=f)
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print(" .TWO_CYCLE_ALU(1)", file=f)
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print(" ) main_b (", file=f)
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print(" .clk(clk),", file=f)
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print(" .resetn(resetn),", file=f)
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print(" .domem(domem_b)", file=f)
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print(" );", file=f)
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print("", file=f)
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print(" task check_reg;", file=f)
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print(" input [4:0] n;", file=f)
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print(" begin", file=f)
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print(" if (main_a.cpu.cpuregs[n] != main_b.cpu.cpuregs[n])", file=f)
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print(" $display(\"Divergent values for reg %1d: A=%08x B=%08x\", n, main_a.cpu.cpuregs[n], main_b.cpu.cpuregs[n]);", file=f)
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print(" end", file=f)
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print(" endtask", file=f)
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print("", file=f)
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print(" task check_mem;", file=f)
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print(" input [31:0] n;", file=f)
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print(" begin", file=f)
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print(" if (main_a.memory[n] != main_b.memory[n])", file=f)
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print(" $display(\"Divergent values for memory addr %08x: A=%08x B=%08x\", n, main_a.cpu.cpuregs[n], main_b.cpu.cpuregs[n]);", file=f)
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print(" end", file=f)
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print(" endtask", file=f)
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print("", file=f)
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print(" initial begin", file=f)
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print(" $dumpfile(\"async_tb.vcd\");", file=f)
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print(" $dumpvars(0, testbench);", file=f)
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print("", file=f)
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for rn, rs in regs_a:
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print(" main_a.%s = %d'b %s;" % (rn, rs, smt.get_net_bin("main_a", rn, "a0")), file=f)
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print("", file=f)
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for rn, rs in regs_b:
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print(" main_b.%s = %d'b %s;" % (rn, rs, smt.get_net_bin("main_b", rn, "b0")), file=f)
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print("", file=f)
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for i in range(1, 32):
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ra = smt.bv2hex(smt.get("a%d_r%d" % (0, i)))
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rb = smt.bv2hex(smt.get("b%d_r%d" % (0, i)))
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print(" main_a.cpu.cpuregs[%2d] = 'h %s; main_b.cpu.cpuregs[%2d] = 'h %s;" % (i, ra, i, rb), file=f)
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print("", file=f)
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for addr, data in memory_data.items():
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print(" main_a.memory['h %08x] = 'h %s;" % (int(addr, 16) >> 2, data), file=f)
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print(" main_b.memory['h %08x] = 'h %s;" % (int(addr, 16) >> 2, data), file=f)
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print("", file=f)
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for i in range(step+1):
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print(" resetn = %d;" % smt.get_net_bool("main_a", "resetn", "a%d" % i), file=f)
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print(" domem_a = %d;" % smt.get_net_bool("main_a", "domem", "a%d" % i), file=f)
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print(" domem_b = %d;" % smt.get_net_bool("main_b", "domem", "b%d" % i), file=f)
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print(" @(posedge clk);", file=f)
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print("", file=f)
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for i in range(1, 32):
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print(" check_reg(%d);" % i, file=f)
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for addr, data in memory_data.items():
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print(" check_mem('h %s);" % addr, file=f)
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print("", file=f)
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print(" @(posedge clk);", file=f)
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print(" @(posedge clk);", file=f)
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print(" $finish;", file=f)
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print(" end", file=f)
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print("endmodule", file=f)
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if words > 0:
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print("running verilog test bench...")
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os.system("iverilog -o async_tb -s testbench async_tb.v async.v ../../picorv32.v && ./async_tb")
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break
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else: # unsat
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smt.write("(pop 1)")
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print("%s Done." % timestamp())
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smt.write("(exit)")
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smt.wait()
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